Processor Clock Driving Circuit with Dynamic Path Selection
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Solution Overview
Problem
Advanced manufacturing processes in mining machine processors lead to a significant deviation between actual working conditions and simulation environments, causing clock driving circuits to fail in meeting design requirements, resulting in reduced processor yield and performance.
Innovation Solution
A processor with a clock driving module comprising multiple clock paths and selectors to provide flexible clock signals with adjustable pulse widths and phases, ensuring timing requirements are met for pipeline stages, particularly using latches as sequential devices to reduce power consumption and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced manufacturing process is used to produce mining machine processor, then manufacturing precision is improved, but device complexity increases leading to deviation between actual working condition and simulation environment
Solution Approach 1:
The patent implements dynamic clock signal adjustment by providing multiple clock paths with different pulse widths and phases, allowing the system to adapt clock parameters based on actual operating conditions. This dynamic adaptation resolves the contradiction by enabling the processor to compensate for manufacturing variations through real-time parameter adjustment rather than relying solely on precise manufacturing.
Solution Approach 2:
The patent changes clock signal parameters (pulse width, phase) to compensate for manufacturing process variations. By providing multiple clock paths with different parameters and selecting appropriate paths based on actual conditions, the system adjusts parameters to maintain timing requirements despite manufacturing complexity and deviations.
2Device complexity
If fixed clock driving circuit is used in design stage, then device complexity is reduced, but reliability deteriorates due to deviation between simulation and actual working conditions
Solution Approach 1:
The patent transforms the fixed clock driving circuit into a dynamic system with multiple selectable clock paths. Each path provides clock signals with different pulse widths and phases, allowing the system to adapt to actual working conditions and maintain reliability despite deviations from simulation environments.
Solution Approach 2:
The patent introduces parameter variability in clock signals by providing multiple paths with different pulse widths and phases. This allows the system to change clock parameters to match actual operating conditions, improving reliability without significantly increasing overall system complexity.
3Adaptability or versatility
If multiple clock paths with different phases are provided, then adaptability is improved to meet timing requirements, but device complexity increases
Solution Approach 1:
The patent implements dynamic clock path selection based on actual operating conditions. The system can dynamically switch between different clock paths with varying pulse widths and phases to meet timing requirements, providing adaptability while managing complexity through conditional selection rather than simultaneous activation of all paths.
Solution Approach 2:
The patent provides multiple clock paths with different parameters (pulse width, phase) to enhance adaptability. By allowing parameter changes in clock signals, the system can meet diverse timing requirements while the complexity is managed through systematic parameter variation rather than fundamentally different circuit architectures.
Data Source
AI summary
The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.