Secured Real Time Clock Module Voltage Tampering Protection

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Solution Overview

Problem

Real time clock modules are vulnerable to tampering, particularly through repetitive alterations of the supply voltage, which can cause them to reset or output invalid commands, and existing monitoring methods are power-consuming and inefficient during low power modes.

Innovation Solution

The implementation of a method to selectively lock and unlock the input ports of a secured real time clock module using a predefined high frequency code, which cannot be generated by tampering with the supply voltage, ensuring the module remains locked during periods outside of authorized programming sequences and low power periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If monitoring of external voltage supply units is implemented to protect the SRTC module, then the reliability of the SRTC module is improved, but the power consumption increases

Engineering Contradiction:
Improveprotection against voltage tamperingVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic monitoring of voltage supply units instead of continuous monitoring. The control unit periodically checks the voltage supply units at predetermined intervals, which reduces power consumption while still providing effective protection against voltage tampering attacks on the SRTC module.

Inventive Principle:
Principle #19Periodic action

2Reliability

If continuous monitoring of voltage supply units is performed, then the protection capability is improved, but the device cannot enter low power modes effectively

Engineering Contradiction:
Improveprotection capabilityVSAvoidlow power mode operation
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The monitoring is performed periodically rather than continuously, allowing the device to enter low power modes between monitoring intervals. This enables the system to maintain protection capabilities while effectively managing power consumption during low power modes.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The control unit autonomously determines when to perform monitoring based on predetermined criteria and intervals, enabling the system to self-manage the balance between protection and power consumption without requiring constant external intervention.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If the SRTC module remains unlocked to allow authorized access, then the ease of operation is improved, but the security against tampering deteriorates

Engineering Contradiction:
Improveauthorized programming accessVSAvoidvoltage tampering vulnerability
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The input ports of the SRTC module are dynamically switched between locked and unlocked states based on authorization status. During authorized programming sequences, the ports are temporarily unlocked to allow access, while at all other times they remain locked to prevent voltage tampering attacks, thus adapting the security state to operational requirements.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8171336B2Method for protecting a secured real time clock module and a device having protection capabilities
Publication Date: 2012.05.01 NXP USA INC
  • US8171336B2 patent drawing
  • US8171336B2 patent drawing
  • US8171336B2 patent drawing

AI summary

A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than the high frequency of the predefined high frequency code.