Voltage Isolation Semiconductor Die Segmentation
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Solution Overview
Problem
Existing isolation solutions, such as capacitive isolation in integrated circuits, restrict the use of semiconductor processes due to the need for complex semiconductor processes like CMOS, limiting flexibility in circuit design and compatibility with other types of circuitry.
Innovation Solution
Implementing isolation circuitry solely on one semiconductor die, allowing for capacitive coupling between dies and enabling the use of different semiconductor processes for the second die, thereby providing complete voltage isolation without the need for isolation circuitry on both dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitive isolation barriers are formed using complex semiconductor processes like CMOS, then voltage isolation is achieved, but the flexibility to use different semiconductor processes for different dies is restricted
Solution Approach 1:
The patent divides the isolation function into separate segments: the first semiconductor die contains the isolation barrier circuitry formed using a first semiconductor process, while the second semiconductor die can be formed using a different second semiconductor process. This segmentation allows each die to be optimized independently for its specific function without process compatibility constraints.
Solution Approach 2:
The isolation barrier circuitry is extracted and concentrated onto the first semiconductor die, eliminating the requirement for isolation circuitry on the second die. This extraction allows the second die to be fabricated using any semiconductor process without being constrained by the process requirements of the isolation circuitry.
2Reliability
If isolation circuitry is present on multiple dies, then voltage isolation is provided, but the complexity of the semiconductor process increases
Solution Approach 1:
The patent merges the isolation barrier functionality entirely onto the first semiconductor die, combining the isolation circuitry with the transmitter or receiver circuitry on that die. This consolidation eliminates the need for separate isolation circuitry on the second die, reducing overall device complexity while maintaining effective voltage isolation.
3Ease of manufacture
If the same semiconductor process is used for both dies, then process compatibility is ensured, but the ability to use advanced processes for specific circuit types is limited
Solution Approach 1:
The patent segments the manufacturing process selection by die: the first die can be fabricated using a first semiconductor process optimized for isolation circuitry, while the second die can be fabricated using a second semiconductor process optimized for specific application circuits such as SLIC or POE circuits. This segmentation enables each die to leverage the most appropriate manufacturing process for its function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high voltage isolation (up to 5 kV) and flexibility in using advanced semiconductor processes, enabling the integration of various circuit types like SLIC and POE without process restrictions, while simplifying the fabrication of the second die.
Implementation Method 1
isolation circuitry to provide voltage isolation between the first semiconductor die and a second semiconductor die coupled to it
Data Source
AI summary
In one embodiment, a method includes receiving an input signal in transmitter circuitry of a first semiconductor die and processing the input signal, sending the processed input signal to an isolation circuit of the die to generate a voltage isolated signal, and outputting the voltage isolated signal from the isolation circuit to a second semiconductor die coupled to the first semiconductor die via a bonding mechanism. Note that this second semiconductor die may not include isolation circuitry.