Chip Select Apparatus for 3D Stacked Systems Using Seed-Based ID Generation

The patent uses a copy-based approach where a master ID code is copied and distributed to multiple identical chips through the TSV connection network. Instead of programming unique ID codes into each chip individually (which increases cost), the system creates copies of the same ID code pattern and uses the chip's position in the stack to differentiate them. This resolves the contradiction by maintaining chip identifiability through copying rather than individual programming.

The patent introduces a new dimension of differentiation by using the vertical stack position (layer index) as an additional identifier. Rather than relying solely on unique ID codes programmed into each chip, the system differentiates chips by their position in the 3D stack, combining the copied ID code with the layer index to uniquely identify each chip. This dimensional approach reduces manufacturing cost while maintaining identifiability.

The patent makes the ID code generation logic universal by using the same logic circuit design in every chip. Instead of having unique logic circuits programmed differently in each chip, the same universal logic circuit generates ID codes based on the chip's layer position. This multi-functional approach allows a single logic circuit design to serve all chips in the stack, reducing hardware cost while maintaining differentiation capability through position-based encoding.

Each chip's logic circuit serves itself by automatically generating its unique ID code based on its own position in the stack. The logic circuit uses the layer index (which is inherently available to each chip in the stack) to generate its identification code without requiring external programming or complex hardware. This self-service approach reduces hardware cost by eliminating the need for external ID code programming equipment.

The patent segments the communication task by dividing the stack into different layers with hierarchical control. Instead of having every chip communicate directly with the controller through TSVs (which would require excessive TSV area), the system segments communication into layer-specific operations. Chips in the same layer can communicate more efficiently, and the controller only needs to access specific layers when needed, reducing the TSV area overhead for chips closer to the controller.

The patent introduces intermediate control logic and layer management structures that act as mediators between the controller and remote chips. Instead of direct controller-to-remote-chip communication requiring extensive TSV connections, the intermediary structures manage communication within layers and between layers, reducing the TSV area overhead by eliminating redundant direct connections from the controller to every chip in the stack.