Indistinguishable Complementary Bit Cells for Reverse Engineering Protection
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Solution Overview
Problem
Reverse engineering of integrated circuits poses a significant threat to the semiconductor industry, as attackers can steal and replicate circuit designs, and existing countermeasures are often costly and inefficient for mass production.
Innovation Solution
The implementation of Indistinguishable Complementary Bit Cells (ICBC-X) with field effect transistors having different threshold voltages, which are integrated into RSX latches and slave latches to create a modified RS master latch, making it difficult for attackers to distinguish the logic states and increasing the difficulty of reverse engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RS latches with identical transistors are used, then manufacturing is simple and cost-effective, but the circuit is vulnerable to reverse engineering and metastable states occur during forbidden transitions
Solution Approach 1:
The patent applies local quality by introducing a subtle asymmetry only where needed - specifically in the threshold voltages of the two transistors in the RS latch. The transistors remain virtually identical in structure and layout for camouflage, but have locally differentiated threshold voltages (differing by at least 10 mV) to prevent metastable states and thwart reverse engineering. This localized differentiation maintains overall circuit simplicity while providing security.
Solution Approach 2:
The patent employs asymmetry by deliberately creating a small voltage difference between two otherwise identical transistors. This asymmetric threshold voltage characteristic (Vth1 ≠ Vth2, with difference ≥ 10 mV) breaks the symmetry that would otherwise make the latch vulnerable to reverse engineering and metastable states during forbidden transitions, while keeping the transistors visually indistinguishable.
2Reliability
If transistors with different threshold voltages are implemented, then reverse engineering difficulty increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by modifying the threshold voltage parameter of the transistors. Specifically, it changes the Vth values to be different (difference ≥ 10 mV) while keeping all other transistor parameters identical. This parameter differentiation ensures defined logic states during forbidden transitions without requiring complex structural modifications, making it compatible with standard manufacturing processes.
Data Source
AI summary
According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified RS master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an RS latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified RS master latch in response to an RS latch forbidden input transition has a predetermined defined logic state, forming an RS slave latch having a set input and a reset input and connecting the set input or the reset input of the RS-slave latch to the output of the modified RS master latch.