CMOS Memory Cell Latchup Prevention via Bus Current Limiting
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Solution Overview
Problem
CMOS circuits face latch-up issues due to parasitic bipolar transistors forming a silicon controlled rectifier (SCR) structure, which can lead to high current flow and data loss, particularly as device dimensions decrease and density increases, with existing solutions either increasing memory cell size or affecting circuit speed and being sensitive to processing parameters.
Innovation Solution
Incorporating current-limiting devices along power-supply and ground buses to maintain the parasitic pnpn diode structure in a reverse-biased state, using resistors or field-effect transistors to prevent forward biasing of junctions, thereby preventing latch-up caused by high energy radiation, cosmic rays, or substrate current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If well and substrate taps are incorporated within each memory cell to reduce well and substrate resistances, then latch-up control is improved, but memory cell size increases and device density decreases
Solution Approach 1:
The patent extracts the latch-up prevention function from the individual memory cell level and implements it at the array level by placing current-limiting devices on the power supply and ground buses that serve multiple cells. This removes the need for taps within each cell while maintaining latch-up protection across the entire array.
Solution Approach 2:
The current-limiting devices on the shared power supply and ground buses serve multiple memory cells simultaneously, providing a universal latch-up prevention mechanism that benefits the entire array rather than requiring cell-specific protection circuits.
2Reliability
If low resistance well regions with varied doping profile are formed to reduce current-gain product of parasitic bipolar transistors, then latch-up control is improved, but junction capacitance increases and threshold voltage increases leading to decreased circuit speed
Solution Approach 1:
The patent removes the need for modifying well region doping profiles by implementing latch-up prevention through external current-limiting devices on the power buses, thereby avoiding the unwanted side effects of increased junction capacitance and threshold voltage that would slow down circuit operation.
3Reliability
If current-limiting devices are arranged along power supply and ground buses, then latch-up prevention is achieved without increasing memory cell size, but additional devices are added to the circuit
Solution Approach 1:
The current-limiting devices are placed on shared power supply and ground buses that serve multiple memory cells, so a single device protects many cells simultaneously. This minimizes the overall number of additional components compared to cell-level protection schemes.
Solution Approach 2:
The current-limiting devices act as intermediary elements on the power buses, indirectly protecting memory cells from latch-up conditions without requiring direct modification of the cell structures or addition of complex control logic within each cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents latch-up without increasing memory cell size, reduces sensitivity to fabrication variations, and maintains circuit reliability, allowing for uninterrupted write and read operations while eliminating single event latch-up.
Implementation Method 1
A current limiting device arranged along the power-supply bus may include a resistor or a p-channel field-effect transistor pass gate... configured to maintain a middle junction as reverse-biased such that latch up within the circuit may be prevented
Data Source
AI summary
A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.