Power Gating Circuit With Dual Current Switches For SoC
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Solution Overview
Problem
Power gating circuits in System on Chip (SoC) face challenges in minimizing power consumption and area usage while maintaining effective time delay, as existing time delay circuits are area-intensive and sensitive to variations in process, voltage, and temperature (PVT).
Innovation Solution
A power gating circuit design incorporating a first and second current switch, along with a switching controller that generates a reference voltage and controls the current switches to achieve a greater time delay with reduced area and minimized power consumption, by using a delay buffer and voltage detection control buffer to manage the transition from sleep to active mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a time delay circuit is used in the power gating circuit, then the time delay function is achieved, but the area of the power gating circuit increases significantly
Solution Approach 1:
The patent extracts the time delay function from a dedicated time delay circuit and implements it using the inherent capacitance and resistance characteristics of existing circuit elements (such as the capacitance of node voltages and resistance of transistor channels). This eliminates the need for a separate, area-intensive time delay circuit while maintaining the required delay functionality.
Solution Approach 2:
The patent makes existing circuit elements serve multiple functions: the transistor channels and node capacitances that are part of the normal power switching operation are also used to provide the time delay function. This multi-functionality reduces the overall circuit area by eliminating dedicated delay circuitry.
2Reliability
If a time delay circuit is used to achieve time delay, then the delay function is provided, but the power consumption of the power gating circuit increases
Solution Approach 1:
The patent extracts the time delay function from an active time delay circuit and implements it passively using inherent circuit characteristics. The delay is achieved through the natural charging and discharging of node capacitances through transistor channels, eliminating the need for active delay circuitry that would consume additional power.
Solution Approach 2:
The circuit uses its own inherent capacitance and resistance characteristics to generate the time delay, without requiring external or additional active components. The power gating circuit's own structural elements (transistor channels, node capacitances) provide the delay function, making the system self-sufficient and reducing overall power consumption.
3Area of stationary object
If a simple switching mechanism is used, then the circuit area is reduced, but the time delay becomes sensitive to PVT variations
Solution Approach 1:
The patent employs feedback mechanisms where the switching controller monitors the voltage levels at various nodes and adjusts the switching timing accordingly. The controller uses the voltage information from the circuit's own operation to regulate the power switching, which compensates for PVT variations and stabilizes the time delay without requiring additional area.
Solution Approach 2:
The patent replaces traditional mechanical or dedicated electronic time delay circuits with a voltage-based control mechanism. The switching controller uses voltage level detection and comparison to determine switching timing, substituting a complex delay circuit with a more compact voltage-controlled switching system that is less sensitive to PVT variations.
Data Source
AI summary
A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.