ESD Robust Level Shifter with Blocking Transistors
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Solution Overview
Problem
Existing level shifter designs in advanced CMOS nodes are susceptible to electrostatic discharge (ESD) failures due to low oxide breakdown voltage, particularly in high-speed applications like USB 3.0 and Thunderbolt, where ESD protection is crucial but compromised by the need for high resistance values that hinder performance.
Innovation Solution
The implementation of an inverter type level shifter with blocking PMOS and NMOS transistors that provide additional voltage drops in the event of voltage spikes, increasing the damage threshold of the gate oxides and enhancing ESD robustness without requiring high resistance clamps or resistors, thus protecting the transistors from ESD damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional level shifter designs are used in advanced CMOS nodes, then device scaling and power consumption are improved, but ESD robustness deteriorates due to low oxide breakdown voltage
Solution Approach 1:
The level shifter is divided into multiple voltage domains (first voltage domain and second voltage domain) with separate power supply voltages and ground voltages. Blocking transistors are inserted at domain interfaces to segment ESD protection functionality, allowing each domain to be protected independently while maintaining overall system operation.
Solution Approach 2:
Blocking transistors serve as intermediary elements between different voltage domains. These transistors provide a controlled interface that allows normal signal transmission while blocking harmful ESD voltage spikes, acting as mediators that protect the gate oxide without interfering with legitimate operation.
2Reliability
If high resistance clamps or resistors are used for ESD protection, then gate oxide protection is improved, but performance in high-speed applications deteriorates
Solution Approach 1:
The blocking transistors dynamically adjust their resistance based on operating conditions. During normal operation, they maintain low resistance to preserve high-speed performance. During ESD events, they transition to high resistance states to provide gate oxide protection, achieving both speed and protection requirements.
Solution Approach 2:
The resistance parameter of the blocking transistors is changed based on the voltage conditions. The transistors operate with variable resistance that adapts to the presence of ESD threats, providing high resistance for protection when needed and low resistance for high-speed operation when ESD is not present.
Data Source
AI summary
An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.