Chip ID Assignment in Stacked Semiconductor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor memory apparatus using the TSV scheme faces challenges in efficiently assigning chip IDs, particularly in stacked configurations, which is costly and time-consuming, and requires additional redundancy chips to prevent failure, limiting the effectiveness of chip selection and integration.
Innovation Solution
A semiconductor apparatus with first and second chips, each equipped with operation units that perform arithmetic operations on initial codes to generate operation codes based on repair signals, allowing for the assignment of unique chip IDs, and a method for determining chip status and reassigning IDs to differentiate between normal and failed chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuse cutting is used to assign chip IDs in TSV stacked semiconductor memory, then chip ID assignment is achieved, but the process becomes costly and time-consuming
Solution Approach 1:
The patent replaces the mechanical fuse cutting process with an electrical signal-based chip ID assignment mechanism. Operation units in each chip perform arithmetic operations on initial codes to generate operation codes that serve as chip IDs, eliminating the need for physical fuse cutting and thereby reducing both time and cost while maintaining assignment accuracy
Solution Approach 2:
The patent changes the method of chip ID generation from physical modification (fuse cutting) to computational generation (arithmetic operations on codes). By using operation units to compute chip IDs based on initial codes and repair signals, the system achieves faster and more cost-effective ID assignment without sacrificing reliability
2Reliability
If redundancy chips are added to prevent failure in TSV stacked semiconductor, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent enables chips to self-identify and self-select through their generated operation codes. Each chip independently generates its own ID based on its operation unit's computation, eliminating the need for external redundancy management and reducing overall system complexity while maintaining reliability
Solution Approach 2:
The operation units serve multiple functions: they perform arithmetic operations on initial codes, generate unique chip IDs, and enable chip selection. This multi-functionality reduces the need for separate redundancy management circuits and simplifies the overall device architecture while ensuring reliable operation
3Quantity of substance
If multiple memory chips are stacked in 3D layout to increase capacity, then memory capacity is improved, but chip ID assignment becomes more difficult
Solution Approach 1:
The patent divides the chip ID assignment process into independent segments, where each chip's operation unit independently generates its own ID through arithmetic operations. This segmentation allows parallel ID generation across multiple stacked chips, making the manufacturing process scalable and easier despite increased capacity
Solution Approach 2:
The patent performs chip ID generation as a preliminary action during the manufacturing process itself, using operation units that compute IDs from initial codes before final assembly. This preliminary ID assignment simplifies subsequent manufacturing steps and testing, making the overall process easier despite the complexity of stacking multiple high-capacity chips
Data Source
AI summary
A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.