Asynchronous Full-Adder Using Capacitive Majority Gates at Low Voltage
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Solution Overview
Problem
Existing asynchronous logic circuits using stacks of transistors between power supply rail and ground rail face challenges in low voltage conditions, making it difficult to implement a full-adder effectively.
Innovation Solution
The use of asynchronous circuits with majority and minority gates, implemented using capacitive input circuits with linear or nonlinear dielectric materials, reduces the stack of devices between supply and ground, allowing operation at lower power supply levels and providing higher throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional stacks of transistors are used between power supply rail and ground rail, then the full-adder can be implemented with established technology, but it becomes challenging to operate in low voltage conditions (1V or less)
Solution Approach 1:
The patent transitions from traditional transistor stack architecture to a new dimensional approach using capacitive input circuits with dielectric materials. This dimensional change in circuit topology allows the full-adder to operate reliably at low voltages by utilizing electric field effects in dielectric layers rather than relying on transistor threshold voltage switching, thus resolving the contradiction between low voltage operation and operational reliability
Solution Approach 2:
The patent changes the fundamental operating parameter from transistor threshold voltage control to dielectric breakdown field control. By using capacitive input circuits where the logic state is determined by voltage-induced dielectric polarization rather than transistor switching, the system achieves reliable operation at lower supply voltages, directly addressing the technical contradiction
2Productivity
If traditional asynchronous logic circuits are used, then the circuit can be implemented with standard components, but the area occupied is larger and throughput is lower
Solution Approach 1:
The patent merges multiple traditional logic components into a single integrated capacitive input circuit structure. By combining the input buffering, logic evaluation, and output driving functions into the dielectric-based capacitive circuit, the design achieves higher throughput while reducing the area occupied compared to traditional asynchronous logic circuits that require separate components for each function
Solution Approach 2:
The patent replaces the mechanical transistor switching mechanism with an electric field-based dielectric polarization mechanism. This substitution eliminates the need for physical transistor stack operations, enabling faster response times (higher throughput) and reducing the physical footprint (smaller area) of the logic circuit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in area reduction and higher throughput compared to traditional asynchronous circuits, enabling efficient operation at low voltages and supporting synchronous logic operations.
Implementation Method 1
implemented using capacitive input circuits with linear or nonlinear dielectric materials
Implementation Method 2
implemented using capacitive input circuits with linear or nonlinear dielectric materials
Data Source
AI summary
Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.