Asynchronous Full-Adder Capacitive Gates for Low-Voltage Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing asynchronous logic circuits using stacks of transistors between power supply rail and ground rail face challenges in low voltage conditions, making it difficult to implement full-adders effectively.
Innovation Solution
Asynchronous full-adders utilizing majority and minority gates with capacitive input circuits, including linear or nonlinear dielectric capacitors, reduce the stack of devices between supply and ground, allowing operation at lower power supply levels and enabling area reduction and higher throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional stacks of transistors are used between power supply rail and ground rail, then the full-adder can be implemented with conventional logic, but the circuit cannot operate effectively in low voltage conditions (1V or less)
Solution Approach 1:
The circuit is segmented into separate true and false signal paths, each handled by dedicated majority and minority gates. This segmentation allows each path to be optimized independently for low-voltage operation, avoiding the cumulative voltage drops that occur in traditional stacked transistor configurations.
Solution Approach 2:
The patent replaces the mechanical transistor stacking approach with a field-based logic system using majority and minority gates. These gates use capacitive coupling and voltage threshold detection rather than direct transistor conduction paths, enabling operation at lower voltage levels where traditional transistor stacks fail to maintain proper logic levels.
2Productivity
If traditional asynchronous logic circuits are used, then the circuit can be implemented with standard components, but the area occupied is large and throughput is limited
Solution Approach 1:
The circuit merges the carry-out true and false signal generation into a unified structure using shared majority and minority gates. The carry-out true signal is generated by a majority gate receiving inputs A, B, and carry-in, while the carry-out false signal is generated by a minority gate with the same inputs, allowing compact integration and reducing overall circuit area.
Solution Approach 2:
The patent transitions from sequential signal processing to parallel evaluation by computing both true and false signals simultaneously through the majority and minority gates. This dimensional change in the computational approach enables higher throughput by eliminating sequential dependencies while maintaining compact area through shared gate structures.
3Ease of manufacture
If stacks of transistors greater than 4 transistors are used, then full-adder functionality can be achieved, but implementation becomes challenging in low voltage conditions
Solution Approach 1:
The patent changes the operating parameters by using voltage threshold detection in majority and minority gates rather than relying on transistor conduction thresholds. This parameter change allows the circuit to operate effectively at lower voltage levels (1V or less) where traditional transistor stacks with more than 4 transistors cannot maintain sufficient voltage margins for reliable logic operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed asynchronous circuits operate efficiently at low voltages, achieving a 3× area reduction and 2× higher throughput compared to traditional asynchronous circuits, while supporting synchronous logic operations.
Implementation Method 1
Asynchronous full-adders utilizing majority and minority gates with capacitive input circuits, including linear or nonlinear dielectric capacitors
Data Source
AI summary
Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.