Capacitive Sense NAND Memory Strings for High Density
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Solution Overview
Problem
The challenge in fabricating longer strings of series-connected memory cells in NAND memory devices limits memory storage density due to difficulties in industrial fabrication techniques.
Innovation Solution
The development of advanced integrated circuit structures and methods for forming NAND memory arrays with improved sense line and select gate configurations, including the use of capacitances and GIDL generator gates, allows for the formation of longer strings of series-connected memory cells, enhancing memory storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If common industrial fabrication techniques are used, then manufacturing process is simple, but the number of memory cells in NAND strings is limited
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (e.g., self-aligned dual-patterning, self-aligned triple-patterning) where each step creates a portion of the final pattern. This segmentation allows achieving higher memory cell density (longer NAND strings) by breaking down the complex patterning into manageable steps that can be executed with existing fabrication tools, thus resolving the contradiction between increasing memory cell quantity and maintaining ease of manufacture.
2Quantity of substance
If longer strings of series-connected memory cells are formed, then memory storage density increases, but fabrication challenges increase
Solution Approach 1:
Sacrificial structures (such as sacrificial plugs or sacrificial layers) are formed in advance during the fabrication process. These preliminary structures guide the self-aligned patterning steps and ensure precise alignment of the NAND string components. By performing these preparatory actions beforehand, the manufacturing precision required for longer NAND strings is achieved without requiring higher precision equipment, thus resolving the contradiction between increasing storage density and maintaining manufacturing precision.
3Quantity of substance
If advanced integrated circuit structures are used, then memory storage density increases, but device complexity increases
Solution Approach 1:
Multiple functions are merged into single structures. For example, select gates serve both as transistor gates and as alignment references for subsequent patterning steps. Sacrificial structures serve dual purposes as both patterning templates and etch stop layers. This merging reduces the number of separate components and simplifies the overall device architecture while still achieving high memory storage density through longer NAND strings.
Solution Approach 2:
The patent employs universal structures that perform multiple functions throughout the fabrication process and device operation. The control gates, for instance, serve as both the functional gate for memory cell operation and as alignment references for self-aligned patterning. The select gates function as both transistors for string selection and as etch stop layers during fabrication. This multi-functionality reduces device complexity while enabling higher storage density.
Data Source
AI summary
Apparatus might include a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors, wherein the plurality of series-connected first field-effect transistors are configured to store user data, and wherein a channel of the plurality of series-connected second transistors is capacitively coupled to a channel of a third transistor.