Capacitive Differential Neural Network Circuit for Low-Power Computing
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Solution Overview
Problem
Artificial neural networks face significant challenges with high power consumption due to the increasing number of layers and neurons, leading to enormous arithmetic operations and circuit complexity.
Innovation Solution
A semiconductor device incorporating a hierarchical artificial neural network with capacitive coupling and current-voltage converter circuits to perform differential voltage operations, reducing power consumption by optimizing signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of layers and neurons in the artificial neural network is increased, then the computational capability and processing accuracy are improved, but the power consumption and circuit complexity increase enormously
Solution Approach 1:
The patent replaces conventional von Neumann architecture with in-memory computing using crossbar arrays, where computational operations are performed directly in memory rather than requiring data to be fetched to separate processing units. This substitution of the computational paradigm enables neural network operations to be executed with significantly lower power consumption while maintaining high processing accuracy through parallel hardware implementation
Solution Approach 2:
The patent divides the neural network into multiple layers with specialized processing units for different computational tasks. Each layer performs specific operations (input processing, weight multiplication, bias addition, activation functions) in parallel, segmenting the overall computation to improve efficiency and reduce power consumption per operation while maintaining overall processing capability
2Adaptability or versatility
If the number of layers and neurons in the artificial neural network is increased, then the computational capability is improved, but the circuit complexity and number of arithmetic operations increase enormously
Solution Approach 1:
The patent implements universal processing units that can perform multiple computational functions within a single hardware structure. Each processing unit can execute weight multiplication, bias addition, and activation function operations through configurable switching mechanisms, eliminating the need for separate dedicated circuits for each operation and significantly reducing overall circuit complexity
Solution Approach 2:
The patent merges storage and computation functions into a unified in-memory computing architecture. The crossbar array structure combines weight storage with computational processing, eliminating the need for separate memory access and processing stages. This integration reduces circuit complexity by eliminating data transfer pathways and reducing the number of discrete components required
3Ease of operation
If conventional von Neumann architecture is used, then the programming flexibility is maintained, but the power consumption increases with increasing processing speed requirements
Solution Approach 1:
The patent implements dynamic reconfigurable crossbar arrays with programmable switching elements that can be dynamically adjusted during operation. The switching mechanisms allow the same hardware structure to be reconfigured for different computational patterns and neural network architectures, providing programming flexibility without requiring physical hardware changes or additional processing stages, thus maintaining ease of operation while reducing power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves low power consumption while performing complex neural network operations, enabling efficient signal processing and inference tasks.
Implementation Method 1
the first capacitor has a function of holding a differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current
Data Source
AI summary
A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.