Alternating two sampling capacitors gives buffer and amplifier a full cycle to settle, cutting power use and signal distortion.
Sequential calibration of an adjustable capacitor array compensates comparator delay and temperature drift to keep RC cutoff frequency stable.
A microprocessor-controlled switched-capacitor block lets one ADC circuit switch among amplification, integration, comparison, and modulation.
Multi-point sampling with a segmented capacitor and averaging switch cuts high-frequency image sensor noise without larger circuits or added filters.
A switched dual-integrator AFE digitizes high X-ray current signals while cutting support-circuit power, area, and noise.
A boost bias and quiescent bias scheme helps a VCO reach steady-state quickly, cutting idle power in low duty cycle communication links.
Dynamic element matching in a DAC uses fractional-weight control to cut mismatch-driven errors, THD, glitch energy, and switching rates.
By cancelling the fixed portion of an external inductive capacitor, the circuit measures only the variable capacitance for higher accuracy and IC integration.
Carry-gated clock transmission lets higher-bit counters switch only when needed, cutting continuous counter power use.
Programmable sampling and feedback capacitors let one analog block switch among amplification, integration, comparison, and modulation.
Level-crossing detection and segmented constant-slope ramps reduce delay and virtual-ground noise errors in sample-data circuits.
An integrator feedback loop stabilizes common-mode voltage in pseudo-differential switched-capacitor circuits, reducing drift and power use.
Unequal input and feedback capacitors in a CDS amplifier cut noise power, shrink circuit area, and improve settling time.
Shared decoupling capacitors are switched between logic islands to improve local charge availability, cut power use, and avoid inductive loops.
Multi-phase sampling and charge transfer synchronize PLL control voltage to the reference clock, reducing phase noise in fractional-N synthesis.
Boost and quiescent bias currents help a VCO reach steady state quickly, enabling low-duty-cycle radios to cut idle power use.
A counter and current-steering DAC preserve the integral value through power save mode, avoiding drift and fast restart errors.
A level-crossing detector and waveform generator hold the sampled output at the zero-crossing instant, improving accuracy, noise, and signal range.
Shared coupling capacitors store preamplifier and latch offsets, cutting charge injection noise while preserving comparator resolution and bandwidth.
Clocked capacitor recharging restores level-shift voltage in one cycle, removing memory effects and stabilizing high-speed biasing.
Differential voltage storage in a capacitor enables neural network arithmetic with lower power and less circuit overhead in semiconductor computing.
Differential voltage held in a capacitor replaces conventional neural arithmetic circuits to cut product-sum power use while preserving accuracy.
Segmenting the external capacitor allows cancellation of the fixed portion, resolving the contradiction between measurement precision and IC integration area.
A computing apparatus converts floating-point data into fixed-point format for efficient vector multiplication operations.
An adaptive filter circuit samples transformer reflected voltage using dynamic switching between bypass and RC filtering modes.
Segmented linear control distributes switching wear across elements, preventing capacitance excursions during hot switching transitions.
A flyback converter driver uses a transconductance amplifier to turn on and a comparator to quickly turn off a synchronous rectifier FET.
Bootstrap circuit boosts gate drive voltage to maintain switch compliance across wide common-mode input ranges, preventing charge injection errors.
Cross-coupled differential full-wave rectifiers reduce die area and noise sensitivity in high-speed adaptive equalizers.
Controlled switching circuits balance leakage currents in differential amplifiers, preventing voltage accumulation and maintaining continuous operation.
A notification server retrieves device addresses and transmits alert messages to subscribed IP-enabled devices.
A dual-terminal rectifier device with a gate-controlled conductive channel couples alternating input signals to generate a rectified output.
Passive switched capacitor circuit performs analog Fourier transform, reducing ADC sample rate and dynamic range requirements while maintaining signal fidelity.
A capacitance to voltage sensing circuit converts measured variable capacitance into an output voltage signal using selective charge amplifier coupling.
A switched-mode power supply uses a sinc filter and cyclic integrator to predict output voltage ripple.
Segmented storage elements resolve contradictions between initial setting accuracy and training efficiency by optimizing conductance adjustments.