Sample-and-Hold Capacitor Switching for Full-Cycle Settling
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Solution Overview
Problem
Conventional sample and hold circuits have limited settling time due to non-overlapping tracking and hold modes, leading to higher power consumption and distortion in analog to digital conversion processes.
Innovation Solution
A sample and hold circuit architecture utilizing two or three sampling capacitors, where one capacitor is charged for a full cycle while the other is connected to the amplifier, and then roles are switched, reducing current demands and power requirements by half or more, and incorporating a discharge phase to stabilize capacitor states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sampling capacitor is used with non-overlapping tracking and hold modes, then the circuit operation is simplified, but the settling time is reduced to half a clock cycle requiring higher power consumption
Solution Approach 1:
The patent divides the single sampling capacitor into two separate capacitors (first sampling capacitor and second sampling capacitor). This segmentation allows one capacitor to be charging during the full clock cycle while the other is connected to the amplifier, eliminating the need for non-overlapping modes and reducing power consumption while maintaining full-cycle settling time.
2Ease of operation
If the tracking and hold modes use non-overlapping clock cycles, then the switching control is simplified, but the buffer and output amplifiers have only half a clock cycle to settle requiring higher current capacity
Solution Approach 1:
The patent uses overlapping clock cycles where the first capacitor begins charging during the hold mode of the second capacitor, before the second capacitor is disconnected. This preliminary charging action ensures that both amplifiers have the full clock cycle to settle without requiring complex non-overlapping switching control, thereby reducing the current capacity requirement.
3Device complexity
If a single sampling capacitor is used, then the component count is reduced, but the amplifier must complete charging/discharging within half a clock cycle increasing distortion
Solution Approach 1:
By segmenting the single sampling capacitor into two capacitors, the patent allows each capacitor to be fully charged during the complete clock cycle when connected to the buffer output. This eliminates the half-cycle charging limitation, reducing signal distortion and improving accuracy while maintaining a manageable component count.
4Reliability
If the sampling capacitor is connected to the amplifier output during hold mode, then the sampled voltage is maintained, but the capacitor must discharge quickly during mode switching causing signal distortion
Solution Approach 1:
The patent segments the capacitor system into two capacitors that operate in overlapping cycles. When the first capacitor is connected to the amplifier, the second capacitor is already charged and ready, allowing smooth transition without rapid discharge requirements. This eliminates the distortion caused by quick discharge during mode switching while maintaining reliable voltage throughout the cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture reduces power consumption and distortion by allowing full cycle settling of buffer and output amplifiers, and stabilizes capacitor states, resulting in lower disturbance and faster settling times.
Implementation Method 1
the capacitor C is connected to the output of buffer 102 and will charge to the voltage of the output of buffer 102
Implementation Method 2
switch 110 is closed when clock signal q2 goes high, placing the capacitor C in a feedback path between the output of amplifier 106 and the input of amplifier 106. This will cause the output of the amplifier 106 to swing to the voltage of the capacitor C. This voltage is held at the amplifier 106 output for half cycle of the main clock signal
Data Source
AI summary
A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.