Switch-Capacitor PLL Loop Filter for Uniform Sampling
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Solution Overview
Problem
Phase lock loops, particularly in fractional-N frequency synthesizers, face significant performance degradation due to the non-uniform sampling problem, which results in increased phase noise and inter-modulation of high-frequency components, leading to low-frequency phase noise that cannot be filtered effectively.
Innovation Solution
A phase lock loop method utilizing a switch-capacitor loop filter that operates in a multi-phase manner with non-overlapping phases, where a sampling capacitor integrates current in one phase and transfers charge to a load capacitor in another phase, controlled by timing signals synchronized with the reference clock, effectively reducing non-uniform sampling and phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional loop filter is used in a phase lock loop, then the circuit is simple, but non-uniform sampling occurs causing increased phase noise and performance degradation
Solution Approach 1:
The loop filter function is segmented into multiple non-overlapping phases, with each phase handling specific sampling operations. This segmentation allows uniform sampling to be achieved while managing complexity through structured phase division.
Solution Approach 2:
The loop filter operates in periodic non-overlapping phases that are synchronized with the reference clock. This periodic action ensures uniform sampling timing and eliminates the non-uniform sampling problem that causes phase noise.
2Adaptability or versatility
If fractional-N synthesis is used to achieve frequency flexibility, then adaptability improves, but non-uniform sampling problem becomes significant causing low-frequency phase noise
Solution Approach 1:
The loop filter with non-overlapping phases provides feedback synchronization to the reference clock, ensuring that sampling occurs at uniform intervals. This feedback mechanism maintains phase noise performance while enabling fractional-N synthesis flexibility.
Solution Approach 2:
The loop filter parameters are changed to operate in discrete non-overlapping phases rather than continuous operation. This parameter change transforms the sampling behavior to be uniform and clock-synchronized, eliminating low-frequency phase noise while maintaining frequency flexibility.
3Measurement precision
If UP and DN pulses are generated based on clock edges, then phase detection is achieved, but timing differences cause non-uniform sampling and increased phase noise
Solution Approach 1:
The phase detection and sampling operations are organized into periodic non-overlapping phases that are strictly synchronized with the reference clock. This periodic structure ensures that both UP and DN pulses are sampled at uniform intervals, eliminating timing-induced phase noise.
Solution Approach 2:
The loop filter is configured in advance with non-overlapping phase timing that is pre-synchronized to the reference clock. This preliminary timing arrangement ensures that all subsequent sampling operations occur at uniform intervals, preventing phase noise before it occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces phase noise and improves the tracking accuracy of the phase lock loop by synchronizing the control voltage with the reference clock, alleviating the non-uniform sampling issue and enhancing the overall performance of fractional-N frequency synthesizers.
Implementation Method 1
a sampling capacitor integrates current in one phase
Implementation Method 2
transfers charge to a load capacitor in another phase
Data Source
AI summary
A switch-capacitor loop filter is used to generate a control voltage for a voltage-controlled oscillator (VCO) in a phase lock loop (PLL). The switch-capacitor circuit works in a multi-phase manner including at least two non-overlapping phases: a sampling phase and a transfer phase. During the sampling phase, the current representing the phase difference between the reference clock and the feedback clock of the PLL is integrated by a sampling capacitor. During the transfer phase, the charge stored on the sampling capacitor is transferred to a load capacitor. The timing for controlling the switch-capacitor function is derived from the reference clock.