Correlated Double Sampling Circuit With Averaged Multi-Point Noise Reduction
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Solution Overview
Problem
High frequency noise superimposed on image sensor output signals degrades the Signal-to-Noise (S/N) ratio in image processing circuits, leading to increased circuit size and power consumption when using conventional methods to reduce noise, such as adding low pass filters or increasing the number of sampling circuits.
Innovation Solution
A correlated double sampling circuit where the sampling capacitor is equally divided into N portions and sampled at N points, with an averaging switch to calculate the average value of sampling values, reducing high frequency noise while maintaining similar circuit size and power consumption, and incorporating a clock circuit for variable sampling frequency control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a low pass filter is added to reduce high frequency noise, then the S/N ratio is improved, but the circuit size and power consumption are increased
Solution Approach 1:
The sampling capacitor is divided into N portions (where N is an integer of at least 2), allowing the circuit to perform correlated double sampling at multiple sampling points without adding external low pass filters. This segmentation enables noise reduction through multiple sampling points while maintaining a compact circuit structure.
Solution Approach 2:
The patent introduces variable sampling frequency control through a clock circuit that can adjust the sampling rate dynamically. This allows the system to adapt to different noise conditions and optimize the balance between S/N ratio and circuit complexity without requiring fixed additional filtering components.
2Measurement precision
If the number of sampling circuits is increased to reduce high frequency noise, then the S/N ratio is improved, but the circuit size and power consumption are increased
Solution Approach 1:
Instead of adding multiple separate sampling circuits, the patent segments a single sampling capacitor into N portions that are sampled at N different sampling points. This achieves the noise reduction effect of multiple sampling circuits while using a single capacitor structure, thereby reducing circuit size.
Solution Approach 2:
The patent merges the functionality of multiple sampling circuits into a single sampling capacitor that is divided into N portions. By combining multiple sampling operations into one capacitor structure with multiple sampling points, the circuit size is reduced while maintaining the S/N ratio improvement.
3Measurement precision
If multiple sampling points are used to reduce noise, then the S/N ratio is improved, but the circuit size increases
Solution Approach 1:
The sampling capacitor is segmented into N portions that can be sampled at N different time points. This segmentation allows multiple sampling operations to be performed with a single capacitor, achieving noise reduction without proportionally increasing circuit size.
Solution Approach 2:
The patent transitions from spatial multiplication (adding multiple parallel sampling circuits) to temporal multiplication (sampling at N different time points). This dimensional change from space to time allows multiple sampling points to be achieved without increasing the physical circuit size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces high frequency noise on image sensor output signals to 1/N of the conventional level without increasing circuit size or power consumption, allowing for improved S/N ratio and variable filter characteristics.
Implementation Method 1
a sampling capacitor is equally divided into N portions (where N is an integer of at least 2) so that a feed-through portion of an image sensor output signal is sampled at N sampling points
Data Source
AI summary
A correlated double sampling circuit has a sampling capacitor equally divided into a plurality of portions. In the correlated double sampling circuit, an input signal is sampled at a plurality of sampling points and an averaging switch is closed to obtain an average value of a plurality of sampling values obtained by sampling. High frequency noise superimposed on the input signal is thus reduced and a difference between the average values of the plurality of sampling values obtained by sampling is output.