Capacitor-Based Neural Arithmetic Circuit for Low-Power Product-Sum
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Solution Overview
Problem
Artificial neural networks face significant challenges with high power consumption due to the large number of arithmetic operations required for product-sum operations and activation functions, especially in hierarchical networks with multiple layers and neurons, leading to increased circuit complexity.
Innovation Solution
A semiconductor device is designed with a novel circuit structure incorporating capacitors and current-voltage converters to perform differential voltage operations, reducing power consumption by optimizing the neural network's arithmetic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional arithmetic circuits are used for product-sum operations and activation functions in hierarchical neural networks, then calculation accuracy is maintained, but power consumption increases significantly
Solution Approach 1:
The patent replaces conventional electronic arithmetic circuits with a hybrid system that uses neuromorphic devices (such as resistive memory devices) to perform multiplication operations through analog conductance values, and uses capacitor-based circuits for summation operations. This substitution of traditional electronic computation with physics-based analog computation reduces power consumption while maintaining calculation accuracy for neural network operations.
2Productivity
If the scale of artificial neural network increases with more layers and neurons, then processing capability improves, but the number of arithmetic operations and circuit complexity increase
Solution Approach 1:
The patent segments the neural network computation into distinct functional units: neuromorphic devices for weight storage and multiplication, capacitor arrays for summation, and selective read circuits for activation functions. Each layer of the neural network can be implemented as modular segments that can be independently configured and scaled, reducing overall circuit complexity while maintaining high processing capability.
Solution Approach 2:
The patent designs universal circuit blocks that can perform multiple functions: the same capacitor array structure can perform summation for different neurons, the same neuromorphic device array can store different weight matrices for different layers, and the read circuit can selectively read out different results. This multi-functionality reduces the need for dedicated circuits for each operation, thereby reducing overall device complexity.
3Ease of manufacture
If conventional SRAM-based artificial neural networks are implemented, then circuit integration is achieved, but power consumption increases with larger scale
Solution Approach 1:
The patent changes the fundamental operating parameters from digital switching (SRAM) to analog continuous values (conductance and charge). Neuromorphic devices operate with continuous conductance values that directly represent weight coefficients, and capacitors hold continuous charge values representing summed signals. This parameter change from digital to analog domain enables more energy-efficient computation while remaining compatible with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves low power consumption while performing hierarchical neural network operations, enhancing efficiency and reducing energy demands.
Implementation Method 1
the first capacitor has a function of holding a differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current
Data Source
AI summary
A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.