Split Counter Circuit With Carry-Gated Clocking for Lower Power
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Solution Overview
Problem
Existing counter circuits face increased power consumption due to all flip-flops receiving the same clock signal, regardless of their operation probability, especially when processing higher bit counts, leading to inefficient power usage.
Innovation Solution
A counter circuit design that includes a first counter for lower bits, a second counter for higher bits, and a clock transmission control circuit that selectively supplies the clock signal to the higher-bit counter based on a carry-out signal from the lower-bit counter, reducing the operation rate and power consumption of the higher-bit counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If all flip-flops receive the same clock signal to ensure uniform operation control, then the circuit structure remains simple, but power consumption increases due to unnecessary clock input to higher-bit counters
Solution Approach 1:
The counter circuit is divided into multiple independent counter units (first counter, second counter, third counter) that process different bit ranges separately. Each counter unit has its own clock input that can be independently controlled, allowing the circuit to segment clock distribution according to operational needs and reduce power consumption in higher-bit counters.
Solution Approach 2:
The clock signal distribution is made dynamic through clock control circuits that adjust whether clock signals are supplied to each counter unit based on real-time operational requirements. This dynamic control allows the system to activate or deactivate clock input to specific counters (e.g., second and third counters) when their operations are not required, thereby reducing power consumption adaptively.
2Measurement precision
If higher-bit counters operate at the same rate as lower-bit counters, then counting accuracy is maintained, but power consumption increases due to unnecessary high-frequency operation of higher-bit counters
Solution Approach 1:
Different counter units are assigned different operational frequencies dynamically. Lower-bit counters (first counter) operate at higher frequencies to handle rapid counting changes, while higher-bit counters (second and third counters) operate at lower frequencies or remain inactive when not needed. This dynamic frequency assignment maintains counting accuracy for all bits while significantly reducing power consumption in higher-bit counters.
Solution Approach 2:
Each counter unit is given different operational characteristics according to its specific function. Lower-bit counters receive continuous clock signals for high-speed operation, while higher-bit counters receive clock signals only when carry conditions are met, allowing them to operate at lower effective frequencies. This local differentiation of operational quality ensures accuracy where needed while minimizing power consumption.
Data Source
AI summary
Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit.