Switchable Decoupling Capacitors for Shared Voltage Domains
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Solution Overview
Problem
In integrated circuits, particularly multi-core processor designs, the existing decoupling capacitor systems face challenges in efficiently managing local charge distribution across voltage domains, leading to increased power consumption and potential chip failure due to high costs and undesirable inductive loops.
Innovation Solution
A circuit assembly with a grid capacitor system that allows decoupling capacitors to be dynamically reassigned between voltage domains based on workload, using p-channel and n-channel field-effect transistors to switch capacitors from less active to more active logic islands, thereby optimizing capacitance distribution without significant cost increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are dedicated to specific logic islands, then local charge availability is improved, but device complexity and power management complexity increase
Solution Approach 1:
The patent implements shared decoupling capacitors that can be dynamically assigned to different logic islands based on workload demands. The capacitor array is controlled by control logic that selectively couples capacitors to active logic islands, allowing the same physical capacitors to serve multiple voltage domains. This eliminates the need for dedicated capacitors for each logic island while maintaining adequate local charge availability, thereby reducing device complexity and power management overhead.
2Reliability
If on-die capacitance is incorporated to increase local charge, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple decoupling capacitors into a shared array that serves multiple logic islands. Instead of incorporating expensive on-die capacitance for each logic island, the design merges capacitor resources at a higher level, allowing a single shared capacitor array to provide local charge to multiple voltage domains. This approach maintains reliability by ensuring adequate charge availability near active logic islands while avoiding the high manufacturing costs associated with on-die capacitance implementation.
3Reliability
If discrete decoupling capacitors are used to improve filtering, then power regulation is improved, but inductive loops are created and local charge adequacy deteriorates
Solution Approach 1:
The patent transitions from external discrete decoupling capacitors to on-packaging-layer capacitors that are integrated closer to the logic islands. By moving the capacitor placement to a different spatial dimension (within the packaging layer rather than externally), the design reduces the loop area formed by power traces, thereby minimizing inductive effects while maintaining effective power regulation and filtering. The shared capacitor array is strategically positioned to provide local charge without creating large inductive loops.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances chip performance by ensuring adequate local charge proximity to active logic islands, reducing power consumption, and minimizing chip failure rates while maintaining cost-effectiveness.
Implementation Method 1
p-channel and n-channel field-effect transistors to switch capacitors from less active to more active logic islands
Data Source
AI summary
A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.