Computing Apparatus Floating-Point to Fixed-Point Conversion
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Solution Overview
Problem
Traditional general-purpose processing devices like CPUs and GPUs are inefficient for deep learning applications due to low computing performance, making them unsuitable for large-scale deployment of deep learning algorithms, especially in scenarios like data centers, where specialized hardware is needed for better performance and efficiency.
Innovation Solution
A computing method and apparatus that converts floating-point data into fixed-point data within the computing apparatus, allowing for vector and matrix multiplication operations to be performed efficiently, reducing the need for additional conversion resources and improving performance/power consumption ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional general-purpose processing devices (CPU, GPU, DSP) are used for deep learning applications, then device versatility is maintained, but computing performance and efficiency deteriorate
Solution Approach 1:
The patent changes the data representation parameter from floating-point to fixed-point format. This parameter change enables the computing device to achieve higher computing performance and efficiency for deep learning applications while maintaining sufficient precision, effectively resolving the contradiction between computing performance and device versatility
Solution Approach 2:
The patent segments the computing process into distinct stages: floating-point to fixed-point conversion, fixed-point multiplication, and result conversion back to floating-point. This segmentation allows the system to use optimized fixed-point arithmetic for the computationally intensive multiplication operations while maintaining compatibility with standard floating-point interfaces, thus improving computing performance without sacrificing versatility
2Productivity
If floating-point data is used throughout the computing process, then data precision is maintained, but computational overhead increases and efficiency decreases
Solution Approach 1:
The patent applies parameter changes by converting data from floating-point to fixed-point representation during computation. This change reduces computational overhead and improves efficiency while the careful design of the conversion process and the use of appropriate fixed-point precision ensure that information loss is minimized and acceptable
Solution Approach 2:
The patent introduces fixed-point arithmetic as an intermediary representation for the multiplication operation. This intermediary format allows efficient hardware implementation of multiplication while the conversion processes at the boundaries ensure that the final result maintains the required precision, thus resolving the contradiction between computing efficiency and data precision
3Device complexity
If floating-point to fixed-point conversion is performed outside the computing apparatus, then conversion resources are available, but device complexity and overhead increase
Solution Approach 1:
The patent merges the floating-point to fixed-point conversion function with the multiplication operation within the computing apparatus. By combining these functions into a single integrated unit, the patent eliminates the need for separate conversion resources, reduces device complexity, and improves computing performance through streamlined data flow and reduced overhead
Data Source
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AI summary
The present disclosure provides an computing method, apparatus, and a storage medium, and relates to the technical field of computers, and in particular, to the technical field of chips and artificial intelligence. An implementation is: based on a plurality of first floating point numbers of a first vector and a plurality of second floating point numbers of a second vector that are input to a computing apparatus obtaining a plurality of first fixed point numbers and a plurality of first exponents that correspond to the plurality of first floating point numbers, and a plurality of second fixed point numbers and a plurality of second exponents that correspond to the plurality of second floating point numbers; obtaining a fixed point product and a fixed point product exponent corresponding to the fixed point product of each first fixed point number of the plurality of first fixed point numbers and a second fixed point number corresponding to the first fixed point number; obtaining a fixed point inner product calculation result of the first vector and the second vector based on a fixed point product exponent corresponding to each of a plurality of fixed point products; and obtaining, based on the fixed point inner product calculation result, a floating point inner product calculation result in a floating point data format corresponding to the fixed point inner product calculation result.