Digital Integrator Circuit for Drift-Free Power Save Recovery
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Solution Overview
Problem
Conventional integrators in low power applications, such as portable devices, experience value drift and discontinuity when resumed from a power save mode, leading to inaccuracies in analog operations.
Innovation Solution
A digital integrator comprising a comparator, up/down counter, and current-steering digital-to-analog converter, which replicates the integrating function using digital counting, ensuring no loss of integral value when switched off, and rapidly resumes accurate operation upon power resumption, with a pseudo-analog output connected to a circuit node of defined impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional analog integrator is used in low power applications, then power consumption is reduced during power save mode, but the integral value drifts over time and causes discontinuity upon resumption of normal operation
Solution Approach 1:
The patent creates a digital copy of the integrator's state by capturing the integral value in a digital register before entering power save mode. This digital copy preserves the exact integral value without drift, and the analog integrator can be completely powered down. Upon resumption, the digital copy is used to rapidly restore the analog integrator's state, eliminating discontinuity while maintaining power savings.
Solution Approach 2:
The patent replaces the continuous analog integrating mechanism with a digital counting mechanism during power save mode. Instead of relying on the analog capacitor to hold the integral value (which drifts), a digital counter maintains the integral value with perfect accuracy. The system substitutes the analog integration function with a digital equivalent that can be maintained without power.
2Loss of energy
If the integrator is switched off to save power, then energy consumption is reduced, but the integrating function cannot be performed during the power save period
Solution Approach 1:
The patent performs preliminary action by capturing and storing the integral value in a digital register before the power save mode begins. This preparation ensures that when normal operation resumes, the integrator can be rapidly reinitialized with the correct value, minimizing any interruption to the integrating function's availability.
Solution Approach 2:
The patent introduces a digital register as an intermediary that bridges the gap between the analog integrator and the power save mode. This intermediary stores the integral value in digital form, allowing the analog integrator to be powered off while preserving its state. The intermediary enables seamless transition between powered and unpowered states without loss of integrating capability.
3Reliability
If a digital counter is used to replicate the integrating function, then the integral value is preserved without drift during power save mode, but the device complexity increases compared to a simple analog integrator
Solution Approach 1:
The patent makes the digital counter serve multiple functions: it acts as both the integrator during active mode and as the state storage mechanism during power save mode. The same digital counter that performs integration during normal operation also captures and preserves the integral value during power save mode, eliminating the need for separate storage hardware and reducing overall system complexity.
Solution Approach 2:
The patent merges the digital counter's integration function with its state storage function. Instead of having separate analog integrator and digital storage components, the system combines these functions into a unified digital implementation that can operate in both active and power save modes using the same hardware resources.
Data Source
AI summary
An integrator is provided with protection against drift in the value of an integral during power save mode. An N-bit counter (12) is driven by the output of a comparator (11) to provide a digital count representation of the integral. The digital count is fed as an input to a current-steering digital-to-analog converter (14) which provides a current of corresponding analog magnitude to other circuitry, such as to an input stage of an error amplifier. The digital count is maintained during power save mode, preserving the integral value until resumption of normal operation.