Capacitive Sensing Layer Integration in Chip Package Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The traditional process of fabricating fingerprint sensor devices involves complex multi-step patterning and deposition processes, leading to increased production costs and prolonged processing times, making it challenging to package semiconductor chips efficiently.
Innovation Solution
A chip package design that includes a substrate with a capacitive sensing layer and a computing chip, where the capacitive sensing layer features capacitive sensing electrodes and metal wires, and the computing chip is electrically connected to these electrodes, simplifying the packaging process by avoiding complex wiring and maintaining the flatness of the capacitive sensing layer for improved detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-step patterning and deposition processes are used to fabricate fingerprint sensor devices, then the device functionality is achieved, but the production cost increases and processing time is prolonged
Solution Approach 1:
The patent combines the capacitive sensing electrodes and the computing chip into a single integrated structure where the computing chip is formed directly above the capacitive sensing layer. This integration eliminates the need for separate wiring processes to connect the electrodes to the computing chip, thereby reducing processing time and steps while maintaining device functionality.
Solution Approach 2:
The computing chip is formed in advance directly above the capacitive sensing electrodes during the same fabrication process, rather than being added later through complex wiring. This preliminary integration of the computing function into the sensing structure eliminates subsequent wiring steps and reduces overall processing time.
2Reliability
If traditional multi-step patterning and deposition processes are used to fabricate fingerprint sensor devices, then the device functionality is achieved, but the production cost increases
Solution Approach 1:
The patent merges the capacitive sensing layer and computing chip fabrication into a single integrated process. By forming the computing chip directly above the capacitive sensing electrodes in the same fabrication sequence, the patent eliminates the need for additional wiring processes, thereby reducing production complexity and cost while maintaining full device functionality.
3Reliability
If additional wiring processes are performed to connect computing chip to capacitive sensing electrodes, then electrical connection is achieved, but the flatness of capacitive sensing layer is compromised
Solution Approach 1:
The patent combines the capacitive sensing electrodes and computing chip into an integrated structure where the computing chip is formed directly above the sensing layer. This integration provides inherent electrical connection through the shared substrate and conductive layers, eliminating the need for additional wiring processes that would disrupt the flatness of the capacitive sensing layer.
Data Source
AI summary
A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.