Capacitor Array Layout for Matching Dishing Sloping
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Solution Overview
Problem
Conventional capacitor array layouts are susceptible to dishing and sloping, leading to severe unit capacitor mismatch due to chemical mechanical polishing and other process steps, which affect the equality of unit capacitances in integrated circuits.
Innovation Solution
The layout of unit capacitors is optimized by grouping them symmetrically between a center and edge region of the array, using an interconnect structure that couples capacitors into geometrically progressing elements and tiling them into substantially identical sub-arrays to resist dishing and sloping, ensuring equal capacitance across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional capacitor array layouts are used, then manufacturing is simpler, but dishing and sloping cause severe unit capacitor mismatch
Solution Approach 1:
The capacitor array is divided into multiple sub-arrays, each containing a portion of the unit capacitors. This segmentation allows the capacitors to be distributed across different regions of the substrate, reducing the impact of dishing and sloping on any single capacitor while maintaining manufacturing simplicity.
Solution Approach 2:
Unit capacitors are strategically positioned within sub-arrays to achieve local optimization. By controlling the specific locations and orientations of capacitors within each sub-array, the design compensates for local variations in substrate flatness caused by dishing and sloping, improving matching without requiring complex global layout changes.
2Manufacturing precision
If unit capacitors are distributed uniformly across the array, then area utilization is maximized, but dishing and sloping cause capacitance variation
Solution Approach 1:
The array is segmented into sub-arrays that are tiled across the substrate. This segmentation enables capacitance matching by ensuring that capacitors in corresponding positions within each sub-array experience similar process conditions, while still achieving high area utilization through the tiled arrangement.
Solution Approach 2:
Identical sub-arrays are replicated and tiled across the substrate. Each sub-array is a copy of the others, ensuring that capacitors in corresponding positions have matched characteristics. This copying approach maintains area efficiency while achieving precision through repetition of the optimized local pattern.
3Manufacturing precision
If capacitor elements are grouped to resist dishing and sloping, then matching is improved, but interconnect structure complexity increases
Solution Approach 1:
Multiple unit capacitors are merged into capacitor elements by connecting them in parallel or series within each sub-array. This merging approach achieves the desired matching by grouping capacitors that experience similar process variations, while the regular sub-array structure keeps interconnect complexity manageable through repetition.
Solution Approach 2:
The interconnect structure is designed to be universal across all sub-arrays, using the same connection patterns and routing styles in each tile. This universality reduces overall complexity by eliminating the need for custom interconnect designs for each region, while still achieving matching through the consistent grouping of capacitors within each sub-array.
Data Source
AI summary
Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed.