Laminated Chip Capacitor Asymmetric Cover Layer Noise Reduction

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Solution Overview

Problem

Existing laminated chip electronic components generate significant acoustic noise due to vibrations when mounted on printed circuit boards, and existing solutions do not effectively reduce this noise beyond a certain level, particularly when internal electrodes are mounted horizontally.

Innovation Solution

A laminated chip capacitor design with a thicker lower cover layer than upper cover layer, where the central portion of the active layer deviates from the ceramic body's central portion, and a ratio of cover layer thicknesses optimized to reduce acoustic noise, along with an identification portion for distinguishing upper and lower portions, is used to minimize noise generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If internal electrodes are mounted horizontally to the PCB, then acoustic noise is reduced compared to perpendicular mounting, but acoustic noise remains at a certain level or higher and further reduction is needed

Engineering Contradiction:

Improveacoustic noiseVSAvoidnoise reduction effectiveness

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent applies asymmetry by making the lower cover layer thicker than the upper cover layer. This asymmetric structure creates a deviation between the central portion of the active layer and the central portion of the ceramic body, which reduces acoustic noise by preventing resonance. The thickness ratio of the lower cover layer to the upper cover layer is specifically controlled within 2:1 to achieve optimal noise reduction while maintaining electrical performance.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The patent applies local quality by creating a specific structural configuration in the lower cover layer region. The lower cover layer is designed with greater thickness and specific material properties compared to the upper cover layer, creating localized structural characteristics that reduce vibration transmission to the PCB while maintaining overall component functionality.

Inventive Principle:

Principle #3Local quality

2Object-affected harmful factors

If the lower cover layer is made thicker than the upper cover layer, then acoustic noise is reduced, but manufacturing precision requirements increase due to specific thickness ratio constraints

Engineering Contradiction:

Improveacoustic noiseVSAvoidcover layer thickness ratio

Core Design Contradiction:

Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by establishing specific numerical ranges for the thickness parameters. The thickness of the lower cover layer is defined as 2 to 10 times the thickness of the upper cover layer, with the upper cover layer being 1 to 10 μm thick. These parameter specifications provide clear manufacturing targets while achieving the desired noise reduction effect.

Inventive Principle:

Principle #35Parameter changes

3Object-affected harmful factors

If the central portion of the active layer is deviated from the central portion of the ceramic body, then acoustic noise is reduced, but device complexity increases due to asymmetric structure design

Engineering Contradiction:

Improveacoustic noiseVSAvoidasymmetric cover layer structure

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design significantly reduces acoustic noise by controlling the displacement of the central active layer within the ceramic body, ensuring the point of inflection is lower than the solder height, thereby minimizing noise transfer to the PCB, even with varying electrode pad sizes.

Implementation Method 1

When DC or AC voltages are applied to the multilayer capacitor having internal electrodes overlapping with dielectric layers interposed therebetween, a piezoelectric effect takes place between the internal electrodes, generating vibrations.

Methodology Applied

Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS8934215B2Laminated chip electronic component, board for mounting the same, and packing unit thereof

Publication Date: 2015.01.13 SAMSUNG ELECTRO MECHANICS CO LTD

AI summary

A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes covering end portions of the ceramic body in length direction; an active layer in which the internal electrodes are disposed in opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in thickness direction, the lower cover layer thicker than the upper cover layer.