Capacitor Contact via Bond Pad Metallization Etch
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Solution Overview
Problem
Integrated circuits face challenges in passivating and making contact to capacitors positioned above top-level interconnect metal without increasing fabrication costs and complexity, particularly due to the need for additional photolithographic cycles and varying etch rates for different via depths.
Innovation Solution
A layer of dielectric is formed on the capacitor to passivate its edges, and the bond pad via etch process is optimized to etch smaller capacitor vias at a lower rate than larger bond pad vias, allowing for electrical contact without damaging the dielectric layer, using bond pad metallization to connect to the top electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond pad metallization is used to contact the top of the capacitor, then electrical contact is achieved, but additional photolithographic cycles are required increasing fabrication cost and complexity
Solution Approach 1:
The patent combines the capacitor via formation and bond pad via formation into a single etch process step. The etch process is configured to etch through the dielectric layer to form both capacitor vias (smaller diameter, shallower depth) and bond pad vias (larger diameter, deeper depth) simultaneously, eliminating the need for separate photolithographic cycles and reducing fabrication complexity
2Reliability
If the bond pad via etch process etches through the dielectric layer to the top electrode, then electrical contact is made, but the etch rate varies between smaller capacitor vias and larger bond pad vias
Solution Approach 1:
The patent applies local quality by creating vias with different dimensions (capacitor vias are smaller and shallower, bond pad vias are larger and deeper) within the same etch process. The etch process parameters are optimized so that the etch rate naturally varies with via size, allowing simultaneous formation of different via types with appropriate depths and diameters in a single step
3Reliability
If the top electrode thickness is increased to accommodate the bond pad via etch process, then etching can proceed without damaging the dielectric layer, but the capacitor structure becomes more complex
Solution Approach 1:
The patent adjusts the top electrode thickness parameter to an optimal value that allows the bond pad via etch process to reach the top electrode without penetrating through to the dielectric layer. This parameter optimization enables simultaneous via formation with different depths while maintaining dielectric integrity and avoiding additional structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for capacitor passivation and contact without adding cost or complexity to the IC fabrication process, maintaining the advantage of incorporating capacitors on the IC without requiring additional photolithographic operations.
Implementation Method 1
A layer of dielectric is formed on the top surface of the capacitor which overlaps and passivates the edges of the capacitor electrodes
Implementation Method 2
Capacitor vias, which are significantly smaller than the bond pad vias, are etched through the dielectric layer to the top electrode during the bond pad via etch process. The bond pad via etch process exhibits a lower etch rate in the smaller capacitor vias than in the larger bond pad vias.
Data Source
AI summary
A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.