Capacitor Chip Package Layout for Void-Free Underfill Flow
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Solution Overview
Problem
Flip-chip bonding in semiconductor packages is vulnerable to impact and distortion due to thermal expansion coefficient differences between the chip and substrate, requiring under-fill materials for structural stability, but existing under-fill processes may not adequately address these issues.
Innovation Solution
A semiconductor package design featuring a dielectric layer with openings for capacitor chips, connection terminals, dielectric patches, and an under-fill material that compensates for thermal expansion, with dielectric patches adjusting under-fill flow to prevent void formation and enhance structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If flip-chip bonding is used to achieve small package size and high package density, then package size is reduced and package density is improved, but the bonding parts become vulnerable to impact and distortion due to thermal expansion coefficient differences
Solution Approach 1:
An under-fill material is introduced as an intermediary substance between the chip and substrate. This under-fill material has thermal expansion properties that compensate for the difference between chip and substrate, reducing distortion and protecting solder bumps while maintaining the compact flip-chip structure
Solution Approach 2:
The thermal expansion coefficient parameter of the under-fill material is specifically selected to compensate for the mismatch between chip and substrate. By changing the material parameter (thermal expansion coefficient) of the under-fill, the overall structural stability is improved while maintaining the compact package design
2Reliability
If under-fill material is added to protect solder bumps and compensate for thermal expansion, then structural stability is improved, but the under-fill process complexity increases
Solution Approach 1:
The under-fill material is applied before the chip is fully mounted on the substrate. This preliminary action allows the under-fill to be properly distributed and cured in position, ensuring optimal protection and thermal compensation while streamlining the overall manufacturing process
3Manufacturing precision
If dielectric patches are added to adjust under-fill flow and prevent void formation, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Dielectric patches are strategically placed in specific locations where void formation is most likely to occur. These localized modifications to the dielectric structure control under-fill flow precisely where needed, preventing voids without requiring complex changes to the entire package structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves structural stability by ensuring uniform under-fill flow and reducing void formation, enhancing the durability of semiconductor packages.
Implementation Method 1
Flip-chip bonding parts are vulnerable to impact and experience distortion due to a difference in thermal expansion coefficient between the chip and the substrate
Implementation Method 2
dielectric patches adjusting under-fill flow to prevent void formation
Data Source
AI summary
A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.