Capacitor Structure Using Conductive Vias in 3D Memory Arrays
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Solution Overview
Problem
Conventional vertical memory arrays require significant real estate for capacitors, which limits memory density and increases the footprint of semiconductor devices due to the need for stair-step structures that consume additional space for electrical contacts.
Innovation Solution
A semiconductor device with a capacitor structure that extends through a stack of alternating conductive and dielectric materials, utilizing conductive vias to form capacitors in series, reducing the need for direct electrical connections to each conductive material level and minimizing real estate requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stair-step structures are used to electrically contact word line materials, then electrical connection is achieved, but real estate consumption increases significantly
Solution Approach 1:
The patent transitions from a planar two-dimensional contact approach to a three-dimensional vertical contact approach. Conductive vias extend vertically through multiple dielectric layers to contact different word line levels, enabling electrical connection without requiring lateral stair-step structures. This dimensional change allows capacitors to be formed in the vertical dimension rather than consuming horizontal real estate.
Solution Approach 2:
The capacitor structure is nested within the existing memory array architecture. Conductive vias are formed through dielectric layers that already contain word line materials, and capacitor plates are formed by depositing conductive materials around these vias. This nesting approach integrates the capacitor structure within the existing three-dimensional memory array without requiring separate real estate.
2Reliability
If capacitors are formed with direct electrical contacts to word line levels, then electrical coupling is achieved, but the footprint of the semiconductor device increases
Solution Approach 1:
The patent forms capacitors by extending conductive vias vertically through multiple dielectric layers to contact different word line levels at different heights. This vertical three-dimensional contact approach replaces traditional lateral two-dimensional contact structures, enabling electrical coupling while minimizing horizontal footprint. The capacitor structure utilizes the vertical dimension of the 3D memory array.
Solution Approach 2:
The same vertical via structures that provide electrical contact to word line materials for memory cell operation are simultaneously used to form capacitor structures. The conductive vias serve dual purposes: providing electrical access to memory cells and forming the electrodes of capacitors for noise reduction and signal coupling.
3Productivity
If memory density is increased using vertical memory arrays, then more transistors fit in unit area, but capacitor real estate requirements become more constrained
Solution Approach 1:
The patent utilizes the vertical dimension of the 3D memory array to form capacitors. Conductive vias extend vertically through multiple dielectric layers containing word line materials at different heights. Capacitor plates are formed by depositing conductive materials around these vertical vias, creating three-dimensional capacitor structures that do not consume additional horizontal real estate.
Solution Approach 2:
The patent merges the capacitor formation process with the existing memory array fabrication process. The same alternating dielectric and conductive material layers that form the memory array are also used to form the capacitor structures. Conductive vias formed for memory cell access are simultaneously used as capacitor electrodes, eliminating the need for separate capacitor real estate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased memory density and reduced footprint by utilizing existing materials in the memory array, achieving higher capacitance without the need for additional space, and maintaining electrical stability at high voltages.
Implementation Method 1
each conductive via comprising a second conductive material extending through the stack within another dielectric on a sidewall of the conductive via
Data Source
AI summary
A semiconductor device includes a capacitor structure. The capacitor structure comprises conductive vias extending through openings in a stack of alternating dielectric materials and first conductive materials, each conductive via comprising a second conductive material extending through the openings and another dielectric material on sidewalls of the openings, first conductive lines in electrical communication with a first group of the conductive vias, and second conductive lines in electrical communication with a second group of the conductive vias. Related semiconductor device, electronic systems, and methods are disclosed.