Capacitor Lower Electrode Layout for Etching Uniformity

Solution Overview

Problem

The uniformity of dielectric and metallization layers in semiconductor devices is challenging to maintain, particularly in central and peripheral regions, affecting the capacitance of capacitor structures during the etching process.

Innovation Solution

A semiconductor device design featuring a substrate with a lower and upper supporting layer, where the lower electrode has distinct vertical lengths, and a method involving sacrificial layers and temperature-controlled etching to optimize the formation of capacitor structures, ensuring complete removal of sacrificial layers and enhancing capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If multiple etching processes are performed to pattern dielectric and metallization layers, then capacitor structures can be formed, but uniformity of layers in central and peripheral regions deteriorates

Engineering Contradiction:

Improvecapacitor structure formationVSAvoidlayer uniformity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by implementing different etching conditions for central and peripheral regions of the substrate. The central region undergoes etching at a first set of conditions while the peripheral region undergoes etching at a second set of conditions, allowing each region to achieve optimal layer removal and uniformity according to its specific requirements.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes etching parameters (such as temperature, pressure, gas flow rates, or chemical composition) between central and peripheral regions. By adjusting these parameters locally, the process achieves better layer uniformity and removes sacrificial layers completely in each region without compromising the other.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If standard etching processes are used, then manufacturing is simplified, but complete removal of sacrificial layers cannot be achieved

Engineering Contradiction:

Improveetching process simplicityVSAvoidsacrificial layer removal completeness

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by implementing different etching conditions for central and peripheral regions of the substrate. The central region undergoes etching at a first set of conditions while the peripheral region undergoes etching at a second set of conditions, allowing each region to achieve optimal layer removal and uniformity according to its specific requirements.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes etching parameters (such as temperature, pressure, gas flow rates, or chemical composition) between central and peripheral regions. By adjusting these parameters locally, the process achieves better layer uniformity and removes sacrificial layers completely in each region without compromising the other.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the electrical properties of semiconductor devices by ensuring uniformity and complete removal of sacrificial layers, thereby increasing capacitance and addressing the uniformity issues in etching processes.

Implementation Method 1

performing an etching process to remove the lower supporting layer

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS20240006474A1Method for manufacturing semiconductor device including capacitor structure having lower electrode with different lengths

Publication Date: 2024.01.04 NAN YA TECH

AI summary

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a lower supporting layer on the substrate; forming an upper supporting layer on the lower supporting layer, wherein the upper supporting layer defines an opening; and forming a lower electrode within the opening of the upper supporting layer, wherein the lower electrode has a first portion with a first vertical length and a second portion with a second vertical length different from the first vertical length.