Multilayer Capacitor Electrode Geometry for High Capacitance Density
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Solution Overview
Problem
Current multilayer capacitors face limitations in increasing capacitance due to challenges in developing high-permittivity materials and reducing dielectric layer thickness, while also requiring miniaturization and increased mounting density on circuit boards.
Innovation Solution
The design includes a capacitor with a body of stacked dielectric layers and internal electrodes of alternating polarity, with insulating regions to increase the overlapping area between electrodes, allowing for enhanced capacitance without reducing dielectric or electrode thickness, and a circuit board configuration to accommodate this structure for reduced mounting area and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of dielectric layers and internal electrodes is reduced to increase the number of stacked layers, then capacitance increases, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent changes the geometric parameters of the internal electrodes from conventional rectangular shapes to shapes with extended overlapping areas. Specifically, the internal electrodes are designed with protruding portions that extend beyond the dielectric layers in certain regions, creating additional overlapping areas that contribute to capacitance without requiring reduction of dielectric layer thickness. This parameter change allows maintaining thicker dielectric layers while achieving higher capacitance.
2Quantity of substance
If the overlapping area of internal electrodes is increased to enhance capacitance, then capacitance increases, but the mounting area and mounting height increase
Solution Approach 1:
The patent utilizes the vertical dimension (stacking direction) more effectively by creating multi-level overlapping structures. The internal electrodes are designed with protruding portions that extend in the vertical direction and overlap with adjacent dielectric layers and electrodes at different heights. This three-dimensional electrode configuration increases the effective overlapping area without proportionally increasing the horizontal mounting footprint, thereby achieving higher capacitance density.
3Quantity of substance
If the number of stacked dielectric layers is increased to enhance capacitance, then capacitance increases, but the mounting height increases
Solution Approach 1:
The patent implements a nested structure where internal electrodes with protruding portions are embedded within and extend beyond the boundaries of dielectric layers. The electrodes are strategically positioned to overlap with multiple dielectric layers simultaneously, creating a nested arrangement where conductive elements are embedded within insulating layers in a space-efficient manner. This nesting approach maximizes the number of effective capacitive interfaces without proportionally increasing the overall stack height.
4Quantity of substance
If high-permittivity materials are used to increase capacitance, then capacitance increases, but material development difficulty and cost increase
Solution Approach 1:
The patent achieves higher capacitance by changing the geometric parameters of the capacitor structure rather than relying solely on material permittivity. By designing internal electrodes with extended overlapping areas and optimizing their spatial arrangement, the patent increases the effective capacitance-forming area. This approach allows using conventional dielectric materials with standard permittivity values while achieving enhanced capacitance performance through improved geometry, thereby avoiding the complexities of developing and manufacturing high-permittivity materials.
Data Source
AI summary
A capacitor includes a body including a plurality of dielectric layers, first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, and first and second insulating regions. The first insulating region is disposed in each of the first internal electrodes and includes a first connection electrode disposed therein. The second insulating region is disposed in each of the second internal electrodes and includes a second connection electrode disposed therein. The products D1×Td and D2×Td are greater than 20 μm2, where Td is a thickness of the dielectric layer, and D1 and D2 are widths of the first and second insulating regions, respectively.