Capacitor Upper Electrode Grain Control via Silicon Seed Layer
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Solution Overview
Problem
Conventional methods for forming cylindrical capacitors in semiconductor devices result in large grain sizes of p-type polysilicon germanium upper electrodes, leading to void formation between the dielectric layer and the upper electrode, which deteriorates electrical characteristics.
Innovation Solution
A capacitor structure with a dual-layer upper electrode structure, where the second upper electrode is formed using silicon and silicon germanium layers doped with p-type impurities, utilizing one layer as a seed for the other to control grain growth and prevent void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a p-type polysilicon germanium layer is directly formed on the dielectric layer without a seed layer, then the manufacturing process is simpler and faster, but the grain size increases undesirably and voids are generated between the dielectric layer and upper electrode
Solution Approach 1:
A silicon layer is formed as a seed layer on the dielectric layer before forming the p-type polysilicon germanium layer. This preliminary seed layer provides a controlled surface for subsequent material deposition, enabling fine grain growth in the upper electrode while maintaining manufacturing efficiency.
Solution Approach 2:
The silicon seed layer acts as an intermediary between the dielectric layer and the p-type polysilicon germanium layer. This intermediate layer facilitates proper adhesion and controls grain nucleation, preventing direct contact issues that would lead to void formation while maintaining process simplicity.
2Ease of manufacture
If the p-type polysilicon germanium layer has relatively large grains to simplify formation, then the manufacturing process is easier, but voids are generated between the dielectric layer and upper electrode deteriorating electrical characteristics
Solution Approach 1:
The silicon seed layer is formed in advance to control the nucleation and growth of grains in the p-type polysilicon germanium layer. This preliminary structure enables the formation of fine-grained upper electrodes through standard deposition processes, maintaining ease of manufacture while ensuring good adhesion and electrical characteristics.
Solution Approach 2:
The introduction of a silicon seed layer changes the physical and chemical parameters of the substrate surface, creating optimal conditions for fine grain growth in the subsequent p-type polysilicon germanium layer. This parameter change enables controlled grain size without complicating the overall manufacturing process.
3Device complexity
If a single-layer upper electrode is used to reduce device complexity, then the structure is simpler, but grain growth cannot be controlled leading to void formation
Solution Approach 1:
The upper electrode is segmented into two functional layers: a silicon seed layer for grain control and a p-type polysilicon germanium layer for electrical performance. This segmentation allows each layer to perform its specific function optimally while maintaining overall structural simplicity.
Solution Approach 2:
The upper electrode structure uses composite materials consisting of silicon and p-type polysilicon germanium. This composite approach combines the grain-nucleation properties of silicon with the electrical characteristics of polysilicon germanium, achieving both fine grain control and good electrical performance without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces undesirable grain growth and voids, enhancing the electrical characteristics of the capacitor by forming a more uniform and effective upper electrode structure.
Implementation Method 1
the second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities
Data Source
AI summary
Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities. The upper electrode structure may be formed without generating voids between the dielectric layer and the upper electrode structure. The capacitor and the semiconductor device having the upper electrode structure may have improved electrical characteristics.