Capacitor Lower Electrode Formation via Masked Etching

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Solution Overview

Problem

The conventional method of forming a lower electrode for capacitors in semiconductor memory devices results in an excessive etch phenomenon due to differing etch rates of sacrificial and mold oxide layers, leading to leaning hole defects and reduced production yields.

Innovation Solution

The method involves forming a mold oxide layer with unevenly etched sidewalls, depositing conductive and sacrificial oxide layers, and using a mask to prevent excessive etching, ensuring the sacrificial oxide layer is not etched prematurely, thereby controlling the etching process to minimize interlayer insulating layer etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a sacrificial oxide layer is deposited between conductive layers to form a capacitor lower electrode, then the capacitor structure can be formed, but the sacrificial oxide layer is etched faster than the mold oxide layer causing excessive etching of the lower interlayer insulating layer

Engineering Contradiction:
Improvecapacitor lower electrode formationVSAvoidetch rate control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a protective mask layer on the mold oxide layer before the etching process. This mask layer is deposited in advance to prevent the etching solution from reaching and excessively etching the lower interlayer insulating layer through the sacrificial oxide layer. The mask layer is then removed after the etching is complete, having served its protective function throughout the process.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the sacrificial oxide layer has a higher etch rate than the mold oxide layer, then the etching process can proceed, but the etch solution penetrates to the lower interlayer insulating layer causing leaning hole defects

Engineering Contradiction:
Improveetching process efficiencyVSAvoidhole structure integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies beforehand cushioning by introducing a mask layer that acts as a cushion or barrier between the etching solution and the lower interlayer insulating layer. This mask layer absorbs or blocks the excessive etching action that would otherwise penetrate through the rapidly-etched sacrificial oxide layer and damage the lower interlayer insulating layer, preventing leaning hole defects before they occur.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If the etch solution is absorbed by the conductive layer surface, then the etching process continues, but the etch solution reaches the lower interlayer insulating layer causing excessive etch phenomenon

Engineering Contradiction:
Improveconductive layer depositionVSAvoidexcessive etching
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent applies the intermediary principle by introducing a mask layer as a mediator between the etching solution and the lower interlayer insulating layer. This mask layer intercepts the etching solution that has been absorbed by the conductive layer surface, preventing it from penetrating further down to etch the lower interlayer insulating layer excessively. The mask layer serves as an intermediate barrier that controls the etching process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the excessive etch phenomenon and leaning hole defects, enhancing the production yield of semiconductor memory devices by maintaining the integrity of the lower electrode structure.

Implementation Method 1

a portion of a lower structure for forming a capacitor lower electrode on a semiconductor substrate may be etched during processes of patterning and etching the sacrificial oxide layer, using a mask

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

the etch solution is absorbed by the surface of the conductive layer and reaches a lower interlayer insulating layer

Methodology Applied
Scientific EffectAbsorption: Absorption (physical)

Data Source

PatentUS7629262B2Method of forming a lower electrode of a capacitor
Publication Date: 2009.12.08 SAMSUNG ELECTRONICS CO LTD
  • US7629262B2 patent drawing
  • US7629262B2 patent drawing
  • US7629262B2 patent drawing

AI summary

In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.