Capacitor Placement in Gate Driving Circuits for Narrow Border Displays

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Solution Overview

Problem

Conventional display panels face challenges in achieving a narrow border design due to the additional width contributed by capacitors in gate driving circuits, which hinders the reduction of border width and affects display efficiency.

Innovation Solution

The capacitors are strategically arranged above or below the signal lines in the array substrate, eliminating their contribution to the border width and allowing for a more compact design by integrating them within the signal line regions, thereby reducing the overall border width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If capacitors are arranged in conventional gate driving circuits, then the gate driving circuit function is achieved, but the border width increases

Engineering Contradiction:
Improveborder widthVSAvoidgate driving circuit function
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The capacitor is moved from a planar arrangement to a three-dimensional arrangement by placing it above or below the signal line, utilizing the vertical dimension to eliminate the capacitor's contribution to border width while maintaining its electrical function

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor is nested within the signal line region by positioning it above or below the signal line, allowing the capacitor to occupy space that does not increase the border width while still performing its function

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS9496288B2Array substrate, display panel and display apparatus
Publication Date: 2016.11.15 SHANGHAI TIANMA MICRO ELECTRONICS CO LTD
  • US9496288B2 patent drawing
  • US9496288B2 patent drawing
  • US9496288B2 patent drawing

AI summary

An array substrate, a display panel and a display apparatus are provided. The array substrate includes a display region and a non-display region. The non-display region is provided with multiple gate driving circuits and multiple signal lines disposed outside the gate driving circuits. Each gate driving circuit includes at least one Thin Film Transistor and at least one capacitor. The capacitor includes a first plate and a second plate, and the capacitor is located above or below the signal lines. Since the capacitor is not arranged in a gate driving circuit region, a size of the gate driving circuit may be reduced. Accordingly, a width of a border of the display apparatus is further reduced, thereby achieving a narrow border design.