Multilayer Ceramic Capacitor Lead Geometry for Low ESL Mounting

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Multilayer ceramic capacitors with high ESL values can lead to instability in high-frequency power supply circuits and improper connections due to tilted mounting and inadequate electrode thickness, causing open failures and insufficient capacitance.

Innovation Solution

A multilayer ceramic capacitor design with optimized lead electrode lengths and thicknesses, where the length of the third lead electrode is between 0.5 and 0.83 times the length of the first and second lead electrodes, reducing ESL and preventing tilted mounting by ensuring proper connection to the mounting land.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the width of the third lead is greater than the width of the first and second leads, then the ESL is reduced, but the thickness of the third outer electrode becomes greater, causing tilted mounting and improper connections

Engineering Contradiction:
ImproveESL reductionVSAvoidmounting precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by precisely controlling the width of the third lead within a specific range (0.5 to 0.83 times the width of the first and second leads). This parameter optimization allows the third outer electrode to maintain adequate thickness for proper mounting connections while still achieving ESL reduction, thus resolving the contradiction between ESL performance and mounting precision.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the width of the first and second leads are extremely small, then the ESL is reduced, but the printing limit is exceeded, causing improper printing and connection

Engineering Contradiction:
ImproveESL reductionVSAvoidprinting feasibility
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent resolves this contradiction by establishing a lower bound for the lead width parameters. By specifying that the first and second leads must maintain sufficient width (with the third lead being 0.5 to 0.83 times their width), the design ensures that printing processes can adequately form the electrodes while still achieving ESL reduction through optimized geometry.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11830675B2Multilayer ceramic capacitor
Publication Date: 2023.11.28 MURATA MFG CO LTD
  • US11830675B2 patent drawing
  • US11830675B2 patent drawing
  • US11830675B2 patent drawing

AI summary

A multilayer ceramic capacitor includes a multilayer body, a first outer electrode on a first main surface closer to a first end surface, a second outer electrode on the first main surface closer to a second end surface, a third outer electrode on the first main surface between the first outer electrode and the second outer electrode, a first inner electrode layer connected to the first outer electrode and the second outer electrode via a first lead electrode and a second lead electrode, and a second inner electrode layer connected to the third outer electrode via a third lead electrode. When a length of the first lead electrode and a length of the second lead electrode in the length direction are each denoted by a, and a length of the third lead electrode in the length direction is denoted by b, b/a is about 0.5 to about 0.83.