Capacitor Sidewall Extension for High-Density Memory Cell Area
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Solution Overview
Problem
The miniaturization of semiconductor memory cells reduces capacitor capacitance, leading to errors in data reading and unintended erasure due to radiation, as the area of the capacitor is minimized.
Innovation Solution
The semiconductor device incorporates a capacitive film with sidewall and active region covering portions, utilizing element isolation grooves to increase the area of the capacitive film without significantly expanding on the semiconductor layer, thereby enhancing capacitor capacitance. This configuration includes a transistor element connected to the capacitor for reliable data operations and forms a memory cell array with high integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the capacitor area is reduced to miniaturize the memory cell, then the memory cell size is reduced, but the capacitance per memory cell is reduced
Solution Approach 1:
The patent utilizes the sidewall surface of the element isolation groove as an additional dimension for forming the capacitive film. Instead of only expanding the capacitor area on the semiconductor layer surface, the capacitive film is extended along the vertical sidewall surface of the groove, effectively increasing capacitance without proportionally increasing the planar footprint of the memory cell.
Solution Approach 2:
The capacitive film is nested within the element isolation groove structure, utilizing the groove's sidewall surface. The electrode film is then formed on top of the capacitive film, creating a nested configuration where the capacitor elements are integrated within the existing groove structure rather than occupying additional lateral space.
2Area of moving object
If the capacitor area is reduced, then the memory cell size is reduced, but errors occur in reading out stored information
Solution Approach 1:
By extending the capacitive film onto the sidewall surface of the element isolation groove, the patent increases the effective capacitance area without increasing the lateral dimensions. This maintains sufficient capacitance for reliable data storage and reading operations while keeping the memory cell compact.
3Area of moving object
If the capacitor area is reduced, then the memory cell size is reduced, but unintended erase operation occurs due to radiation
Solution Approach 1:
The patent increases capacitance by utilizing the vertical sidewall surface of the element isolation groove. This three-dimensional configuration provides greater capacitance per unit area, creating a more robust capacitor that can maintain stored information more reliably under radiation exposure without requiring larger lateral dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases capacitor capacitance without area expansion, ensuring reliable data storage and operations in high-density memory cells, even under radiation exposure.
Implementation Method 1
a capacitive film having a sidewall covering portion that covers a sidewall of the element isolation grooves
Implementation Method 2
an electrode film laminated on the capacitive film
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film.