Capacitor Structure Inhibiting Parasitic Fringe Capacitance
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Solution Overview
Problem
Conventional capacitor structures in integrated circuits face limitations in achieving ultra-low capacitance values due to parasitic capacitance across electrodes and the inefficiency of serial coupling multiple capacitors, which restricts device miniaturization and manufacturability.
Innovation Solution
A capacitor structure is formed with a first ring electrode in an inter-level dielectric layer on a substrate, an inner electrode within the ring electrode, and a capacitor dielectric separating them, which inhibits parasitic fringe capacitance through a scyphoid geometry, allowing for the creation of low-capacitance capacitors within a single layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor structures with two metal plates and insulator are used, then desired capacitances can be achieved, but the plates require significant surface area which limits device miniaturization
Solution Approach 1:
The patent transitions from a conventional planar parallel-plate capacitor configuration to a vertically stacked three-dimensional structure. Multiple capacitor elements are arranged in vertical layers within an inter-level dielectric, utilizing the third dimension (height/depth) to achieve the required capacitance without increasing the lateral footprint on the substrate. This dimensional change allows compact integration while maintaining desired capacitance values.
2Quantity of substance
If transverse metal lines or fingers are used to integrate capacitors, then capacitance can be achieved, but manufacturability and capacitance ranges are limited as devices decrease in size
Solution Approach 1:
The patent merges the capacitor structure with the inter-level dielectric layer and surrounding transistor structures. The capacitor electrodes are formed using the same metal layers and patterning processes as the transistor interconnects, and the inter-level dielectric serves dual purposes as both insulation and capacitor dielectric. This integration eliminates the need for separate capacitor fabrication processes, improving manufacturability while enabling a broader range of capacitance values through variable electrode geometry and stacking configurations.
3Quantity of substance
If serial coupling of multiple capacitors is used to reduce effective capacitance, then lower capacitance can be achieved, but available space in the device structure is reduced
Solution Approach 1:
The patent segments the capacitor structure into multiple discrete capacitor elements that can be independently configured. By dividing the total capacitance into separate segments arranged in series or parallel combinations, the effective capacitance can be precisely controlled. The segmented design also allows optimization of each individual capacitor element's geometry to minimize parasitic effects while maintaining the desired effective capacitance value.
4Quantity of substance
If conventional capacitor electrodes are used, then capacitance can be achieved, but parasitic capacitance across electrodes through overlying and underlying device layers prevents ultra-low capacitance values
Solution Approach 1:
The patent extracts the capacitor structure from the conventional planar configuration and relocates it to a vertical stacking arrangement within the inter-level dielectric. This extraction removes the capacitor electrodes from direct interaction with overlying and underlying device layers that create parasitic capacitance paths. The vertical isolation provided by the inter-level dielectric effectively eliminates parasitic coupling, enabling ultra-low capacitance values down to 0.5 fF or lower.
Data Source
AI summary
Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.