Capacitor Stack Formation Using Trench-Box Cavities
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Solution Overview
Problem
Current methods for producing 3D capacitors, such as MIM capacitors, face challenges including capacity loss due to chemical-mechanical planarization and cumbersome processes, especially when dealing with high-dielectric materials, which complicate the etching process and increase costs.
Innovation Solution
A method involving the formation of cavities in a substrate with trenches and boxes, where the box mouth is larger than the trench mouth, allowing for a capacitive stack to be deposited on both the cavity walls and the substrate surface, enabling optimized CMP polishing and enhanced capacitance while facilitating connections to external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP polishing is used to remove MIM stack at substrate surface, then planarization is achieved, but total capacity is reduced due to loss of surface capacitance
Solution Approach 1:
The invention segments the capacitor structure into two distinct parts: 3D capacitors formed in trenches extending into the substrate, and 2D planar capacitors formed on the substrate surface. This segmentation allows CMP polishing to selectively remove only the planar capacitor material at the surface while preserving the 3D capacitor structures in the trenches, thus achieving planarization without complete loss of surface capacitance. The trench structures act as protective segments that guide the polishing process.
Solution Approach 2:
The invention transitions from a purely 2D planar capacitor configuration to a 3D structure by etching trenches into the substrate. This dimensional change creates vertical capacitance components that extend below the substrate surface, allowing the capacitor to maintain total capacity even when surface material is removed during CMP polishing. The 3D structure adds a depth dimension that compensates for surface area loss.
2Volume of moving object
If trenches are etched for 3D capacitor formation, then space saving and increased developed surface capacity are achieved, but surface capacitance is lost during CMP polishing
Solution Approach 1:
The capacitor system is segmented into vertical 3D capacitor components in trenches and horizontal 2D planar capacitor components on the surface. This segmentation ensures that when CMP polishing removes surface material, the vertical trench capacitors remain intact and continue to contribute to total capacitance, while the planar capacitors are selectively removed to achieve proper planarization for subsequent processing layers.
Solution Approach 2:
The invention creates a composite capacitor system combining 3D trench structures with 2D planar structures, utilizing different spatial configurations of the same MIM capacitor technology. This composite approach allows the system to benefit from both the space-saving vertical integration of 3D capacitors and the ease of planarization provided by 2D capacitors, maintaining total capacity through the combined effect of both structures.
3Quantity of substance
If high-k dielectric materials are used in capacitive stack, then capacitance is increased, but etching process becomes very difficult and complicated
Solution Approach 1:
The invention extracts the problematic etching step for high-k dielectric layers by forming the entire capacitive stack within protected trench structures before any etching operations. The trench walls act as physical masks and protective structures, allowing the high-k dielectric material to be deposited and patterned without requiring subsequent etching of the dielectric layer itself. This extraction of the etching requirement simplifies the manufacturing process while maintaining the high capacitance benefits of high-k materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases total capacity with a non-vertical dimension, preserves surface layer removal for optimized connections, and allows the use of advanced high-k materials without etching complications, resulting in a significant capacitance gain and process efficiency.
Implementation Method 1
3D capacitors, for example MIM (Metal/Insulator/Metal) capacitors
Implementation Method 2
a material with a high dielectric constant of the type known by the term 'high-k'
Implementation Method 3
a planarization, for example, a CMP polishing, acronym for 'Chemical-mechanical planarization'
Data Source
Figure 1
Figure 2a~2b
Figure 2c~2e
AI summary
The invention concerns a method for producing a capacitor, comprising the forming of a capacitor stack in one portion of a substrate (112), said method comprising: the forming of a cavity (165) along the thickness of the portion of the substrate (112) from an upper face of said substrate (112), the depositing of a plurality of layers contributing to the capacitor stack onto the wall of the cavity (165) and onto the surface of the upper face, and a removal of matter from the layers until the surface of the upper face is reached, characterised in that the formation of the cavity (165) comprises the formation of at least one trench (164) and, associated with each trench (164), of at least one box (163), said at least one trench (164) comprising a trench outlet that opens into the box (163), said box (163) comprising a box outlet that opens at the surface of the upper face, the box outlet being shaped so as to be larger than the trench outlet.