Capacitorless DRAM with Vertical GAA Stacking for Stability
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Solution Overview
Problem
Existing semiconductor memory devices face challenges such as noise due to capacitive coupling between a word line and a body, and memory instability leading to false reading and rewriting of storage data, particularly in capacitorless DRAMs.
Innovation Solution
A semiconductor memory device is designed with a gate-all-around (GAA) technology, where memory cells are stacked vertically, using a structure that includes multiple impurity layers, semiconductor layers, and gate conductor layers to perform memory operations through impact ionization and gate-induced drain leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitorless single-transistor DRAM structure is used, then device integration density is improved, but memory stability deteriorates due to high dependency on gate-to-word line coupling and substrate depletion
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to vertical 3D stacking architecture. Multiple memory cells are stacked in the vertical direction using gate-all-around (GAA) nanowire transistors, enabling higher integration density while maintaining electrical isolation between cells through insulating layers, thus improving both density and stability
Solution Approach 2:
The gate electrode completely surrounds the nanowire channel in a cylindrical configuration (gate-all-around structure). This nested arrangement maximizes the gate control over the channel, improving carrier confinement and reducing leakage current, which enhances memory stability while maintaining compact cell size for high density
2Productivity
If vertical stacking of memory cells is implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The vertical stack is divided into discrete memory cell units, each with its own nanowire channel and gate structure. This segmentation allows for modular manufacturing where each cell can be formed through systematic repetition of layer deposition and patterning steps, reducing overall manufacturing complexity despite the 3D architecture
Solution Approach 2:
The patent employs advanced material deposition techniques to create alternating layers of semiconductor and insulating materials with precise thickness control. By adjusting layer thickness parameters and material composition, the vertical stack structure is achieved with controlled electrical properties, enabling high-density stacking while maintaining manufacturability through parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density and high-speed MOS circuit operation with improved memory stability, reduced noise, and wider operational margins by effectively managing carrier generation and retention in the semiconductor layers.
Implementation Method 1
memory write operation is performed by controlling voltage applied to each of the first conductor layer, the second conductor layer, the first gate conductor layer, and the plurality of second gate conductor layers to perform operation of generating electrons and holes in the plurality of semiconductor layers through an impact ionization phenomenon
Implementation Method 2
operation of generating electrons and holes in the plurality of semiconductor layers through an impact ionization phenomenon with current flowing between the plurality of first impurity layers and the plurality of second impurity layers or through gate induced drain leakage current
Implementation Method 3
a plurality of gate insulating layers covering the plurality of respective semiconductor layers, part of the plurality of respective first impurity layers, and part of the plurality of respective second impurity layer; a first gate conductor layer disposed in contact with the plurality of gate insulating layers
Data Source
AI summary
A first insulating layer 21 is disposed on a substrate 20. N+ layers 2 are separated from the insulating layer and in directions horizontal and vertical to the substrate. P layers 1 contact the n+ layers 2 and extend in the horizontal direction. N+ layers 3 contact the p layers 1. Gate insulating layers 4 cover the p layers 1 and part of the n+ layers 2 and 3. Second gate conductor layers 6 are electrically separated from a first gate conductor layer 5 contacting the gate insulating layers 4. A conductor layer 12 contacts the n+ layers 2. A conductor layer 13 contacts the n+ layers 3. A second insulating layer 22 contacts the first gate conductor layer 5, the n+ layers 2, and the conductor layer 12. A third insulating layer 23 contacts the second gate conductor layers 6, the n+ layers 3, and the conductor layer 13.