Capacitor-less DRAM Cell Noise Isolation via Gate Capacitance
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face issues due to strong capacitive coupling between the word line and the floating body, leading to direct noise transmission and erroneous data reading or writing.
Innovation Solution
A semiconductor memory device with a dynamic flash memory cell structure, where the gate capacitance of the first gate conductor layer connected to the plate line wiring layer is made larger than that of the second gate conductor layer connected to the word line wiring layer, to reduce capacitive coupling and noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate conductor layer is connected directly to the word line, then the memory cell can be operated, but strong capacitive coupling causes noise interference and erroneous data reading or writing
Solution Approach 1:
An insulating layer is introduced between the gate conductor layer and the word line wiring layer to act as an intermediary that blocks direct capacitive coupling. This mediator prevents noise transmission from the word line to the floating body while still allowing the memory cell to be controlled through the gate, thereby resolving the contradiction between operational functionality and noise interference.
2Device complexity
If the memory cell uses a single transistor without capacitor, then the device complexity is reduced, but noise from word line directly affects the floating body potential
Solution Approach 1:
The insulating layer serves as a mediator that allows the simplified single-transistor structure to function while blocking the harmful capacitive coupling path. This enables the memory cell to maintain its low-complexity advantage without suffering from direct noise transmission to the floating body.
3Object-affected harmful factors
If the gate capacitance is increased to reduce noise coupling, then the noise interference is reduced, but the device area increases
Solution Approach 1:
Instead of increasing gate capacitance to reduce noise coupling, the insulating layer intermediary provides noise isolation without requiring increased device area. This approach achieves noise reduction through spatial separation and insulation rather than through capacitance scaling, thereby avoiding area expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise interference and provides a sufficient margin between the '1' and '0' potentials, enhancing data retention and reliability in capacitor-less single-transistor DRAMs.
Implementation Method 1
the gate capacitance of the first gate conductor layer connected to the plate line wiring layer is made larger than that of the second gate conductor layer connected to the word line wiring layer, to reduce capacitive coupling and noise interference
Implementation Method 2
a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current
Implementation Method 3
a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current
Data Source
AI summary
A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.