Capacitorless DRAM Cells for Word-Line Coupling Noise Control
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Solution Overview
Problem
Capacitorless single-transistor DRAM memory cells face issues with large capacitive coupling between the word line and the floating body, leading to potential noise during data read or write operations, which causes misreading or erroneous rewriting, making them difficult to implement commercially.
Innovation Solution
A semiconductor memory device with a matrix arrangement of cells, utilizing a vertical semiconductor base body and controlled voltage application to hold and erase positive hole groups, employing separate gate conductor layers with different capacitance ratios to minimize noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless single-transistor DRAM memory cells are used, then device complexity is reduced and packaging density is improved, but capacitive coupling noise between word line and floating body increases, causing misreading or erroneous rewriting
Solution Approach 1:
The patent introduces a charge pump circuit as an intermediary component that actively compensates for capacitive coupling noise. The charge pump generates compensation charges based on the word line voltage changes and injects them into the floating body to counteract the noise effect, thereby resolving the contradiction between simplified memory cell structure and noise reduction
Solution Approach 2:
The patent dynamically adjusts the voltage parameters of the memory cell components (word line voltage, floating body voltage, bit line voltage) during different operation phases (read, write, refresh). By changing these voltage parameters in a controlled manner, the system maintains stable operation despite the presence of capacitive coupling, thus resolving the noise issue while keeping the memory cell structure simple
2Speed
If word line voltage swings during read/write operations, then data access speed is improved, but capacitive coupling transmits voltage swings as noise to the floating body, causing misreading
Solution Approach 1:
The patent implements a feedback mechanism where the charge pump circuit monitors the word line voltage swings and generates corresponding compensation signals. The compensation charges are injected into the floating body in real-time to counteract the noise induced by word line voltage changes, thus maintaining reading accuracy while allowing fast data access
Solution Approach 2:
The system performs refresh operations before data becomes corrupted by capacitive coupling noise. The charge pump proactively compensates for voltage swings during read/write operations, cushioning against potential misreading before it occurs, thereby maintaining both high speed and high reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitive coupling noise, ensuring stable data retention and accurate reading/writing operations by alternately reading storage data through odd and even bit lines, enhancing the practicality of capacitorless DRAM cells.
Implementation Method 1
positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current are held in the semiconductor base body
Implementation Method 2
positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current are held in the semiconductor base body
Data Source
AI summary
A data retention operation of holding positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base body is performed by controlling voltages applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines; and a data erase operation is performed by removing positive hole groups from inside the semiconductor base body by controlling the voltages applied to plate lines, word lines, source line, odd-numbered bit lines, and even-numbered bit lines and lowering a voltage of The semiconductor base body by means of capacitive coupling between the plate lines and word lines. A block is made up of memory cells arrayed in a matrix, and storage data is read from the memory cells in the block alternately to the odd-numbered bit lines and even-numbered bit line.