Capacitorless DRAM Cell Noise Isolation via Tunnel Insulator
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Solution Overview
Problem
Capacitorless single-transistor DRAMs experience strong capacitive coupling between the word line and the floating body, leading to noise transmission during data reading or writing, resulting in erroneous readings and rewrites, which hinders practical implementation.
Innovation Solution
The memory apparatus incorporates a page of memory cells with a semiconductor base material standing upright or horizontally on the substrate, featuring a first and second impurity region, a gate insulating layer, and gate conductor layers. By controlling the voltages applied to these components, holes generated through impact ionization or gate-induced drain leakage are retained or removed, allowing for effective data holding and erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitorless single-transistor DRAM structure is used, then device integration density is improved, but noise transmission from word line to floating body causes erroneous readings
Solution Approach 1:
The patent introduces a tunnel insulating layer as an intermediary between the word line and the floating body. This tunnel insulating layer acts as a mediator that blocks the direct capacitive coupling path, preventing noise from the word line from being transmitted to the floating body while still allowing the structure to function as a capacitorless DRAM cell.
Solution Approach 2:
The patent extracts or removes the direct capacitive coupling path between the word line and floating body by inserting the tunnel insulating layer. This separation takes out the harmful noise transmission pathway while preserving the essential functionality of the capacitorless DRAM structure.
2Speed
If strong capacitive coupling exists between word line and floating body, then write operation speed is improved, but noise interference increases causing data errors
Solution Approach 1:
The tunnel insulating layer serves as a mediator that selectively blocks noise transmission while allowing the write operation to proceed. It mediates between the need for strong coupling for fast writing and the need to prevent noise interference, enabling both requirements to be satisfied simultaneously.
3Stability of the object's composition
If voltage control is applied to retain holes in semiconductor base material, then data holding capability is improved, but device complexity increases
Solution Approach 1:
The patent employs self-service principles where the voltage control mechanism utilizes the inherent electrical characteristics of the semiconductor devices. The control voltages applied to the gate conductor layers and impurity regions exploit the natural hole retention and release mechanisms in the semiconductor base material, achieving stable data holding without requiring additional complex control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise interference from word line voltage oscillations, providing a sufficient margin for the potential difference between written '1' and '0' states, thus enhancing data integrity and enabling practical use of capacitorless DRAMs.
Implementation Method 1
first capacitive coupling between the first gate conductor layer and the semiconductor base material and second capacitive coupling between the second gate conductor layer and the semiconductor base material
Implementation Method 2
holes generated through an impact ionization phenomenon
Implementation Method 3
gate insulating layer in contact with a side face of the semiconductor base material
Data Source
AI summary
A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and further lowering a voltage of the semiconductor base material through capacitive coupling with the first gate conductor layer and the second gate conductor layer.