Capacitorless Memory Cell Using Dynamic Gate Voltage Control
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Solution Overview
Problem
Current memory devices face challenges in improving data retention characteristics and operating margins due to voltage fluctuations in floating body channels, particularly in dynamic random access memory (DRAM) and twin-transistor MOS transistor memory elements, which affect the reliability of logic storage data.
Innovation Solution
A dynamic flash memory cell design that includes a semiconductor base with impurity regions and gate conductor layers, where voltages are controlled to perform page erasing and writing operations, allowing for three-valued or four-valued logic storage data retention by managing hole groups generated through impact ionization, and using a sense amplifier circuit to determine logic storage data during reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single MOS transistor without capacitor is used as memory cell, then device density is improved, but data retention characteristics deteriorate due to voltage fluctuation in floating body channel
Solution Approach 1:
The patent changes the voltage parameters applied to the gate electrodes dynamically during different operations (writing, reading, retaining). By controlling the voltage levels on the first and second gate electrodes, the memory cell can maintain stable floating body channel voltage to improve data retention while preserving the capacitorless high-density structure.
Solution Approach 2:
The patent employs feedback mechanisms through the gate electrodes to control the floating body channel voltage. The gate electrodes provide feedback control to stabilize the channel voltage and prevent excessive voltage fluctuations that would cause data loss, thereby improving retention without adding capacitors.
2Ease of operation
If hole group is discharged from channel to write logic data '0', then writing operation is completed, but operating margin is reduced due to voltage fluctuation
Solution Approach 1:
The patent dynamically changes the voltage parameters of the gate electrodes during the writing operation. When discharging holes to write logic '0', the voltage on the gate electrodes is controlled to minimize voltage fluctuations in the floating body channel, thereby maintaining operating margin while completing the writing operation.
Solution Approach 2:
The patent performs preliminary voltage control on the gate electrodes before and during the hole discharge process. By pre-establishing appropriate voltage levels and maintaining them during the writing operation, the system prevents excessive voltage fluctuations that would reduce operating margin.
3Reliability
If capacitor is added to memory cell to improve data retention, then data retention is improved, but device density is reduced
Solution Approach 1:
The patent extracts the capacitor component from the traditional DRAM structure and replaces it with a capacitorless single-transistor design using a floating body channel. This extraction of the capacitor while maintaining retention functionality through voltage-controlled gate electrodes enables high device density without sacrificing data retention.
Solution Approach 2:
The patent substitutes the mechanical/electrical capacitor storage mechanism with a voltage-controlled floating body channel system. Instead of physically storing charge in a capacitor, the system uses quantum mechanical effects in the floating body channel controlled by gate voltages to achieve data retention, eliminating the need for additional capacitors and increasing density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances data retention and operating margins by effectively managing hole groups within the semiconductor base, enabling higher-density and high-performance memory devices with improved data storage and retrieval capabilities.
Implementation Method 1
a hole group formed by an impact ionization phenomenon or a drain-induced leakage current phenomenon is retained within the semiconductor base
Implementation Method 2
a selected memory cell connected to the selection word line has a floating body channel voltage that fluctuates greatly due to the capacitive coupling between the gate electrode and the channel
Data Source
AI summary
In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity region and a second impurity region at both ends of the semiconductor base, and at least two gate conductor layers. The first impurity region is connected to a source line, the second impurity region to a bit line, one of the two gate conductor layers to a selection gate line, and the other to a plate line. Voltages applied to these lines are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have three-valued logic storage data. A sense amplifier circuit performs determination in an order of logic storage data with a large number of holes in the hole group.