Capacitorless RAM Charge Retention via Band Gap Engineering
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Solution Overview
Problem
Conventional capacitorless RAMs face challenges in retaining electric charges for an adequate period, leading to short refresh cycle times and high power consumption due to the fleeting floating body effect in field effect transistors.
Innovation Solution
A semiconductor device with a field effect transistor featuring a channel body region made of a semiconductor with a specific band gap, where a second semiconductor with a larger band gap is positioned between the channel body and contact regions, increasing the energy barrier and enhancing charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a conventional FBC type RAM uses a single semiconductor material for the channel body region, then the device structure is simple, but the retention time of electric charges is too short leading to high power consumption
Solution Approach 1:
The patent applies composite materials by forming a first semiconductor layer (e.g., SiGe) and a second semiconductor layer (e.g., Si) with different band gaps in the channel body region. The first semiconductor layer with smaller band gap enhances charge accumulation, while the second semiconductor layer with larger band gap reduces carrier generation, thereby extending retention time and reducing power consumption.
2Use of energy by stationary object
If the refresh cycle time is shortened to improve power consumption, then power consumption is reduced, but the retention time becomes insufficient leading to data loss
Solution Approach 1:
The patent changes the band gap parameter of the semiconductor material in the channel body region by using a composite structure of first and second semiconductor layers with different band gaps. This parameter change increases the energy barrier for carrier generation, extends retention time, and allows for longer refresh cycle times with reduced power consumption.
3Force
If a single semiconductor material is used in the channel body region, then fabrication is simpler, but the energy barrier for charge retention is insufficient
Solution Approach 1:
The patent uses composite semiconductor materials with different band gaps (first semiconductor layer with smaller band gap and second semiconductor layer with larger band gap) to create a higher energy barrier for charge retention. The fabrication process includes forming these layers through epitaxial growth or other semiconductor manufacturing techniques, which, while more complex than single-material processes, are compatible with existing technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration lengthens the retention time, reduces power consumption, and allows for nondestructive data reading and faster refresh operations, enabling higher integration and compatibility with logic device fabrication processes.
Implementation Method 1
the field effect transistor includes a first region comprising a first semiconductor having a given band gap and a second region comprising a second semiconductor having a larger band gap than the first semiconductor
Implementation Method 2
the floating body effect of transistor without using a capacitor
Implementation Method 3
when the cell transistor is biased to a saturated state and holes generated by impact ionization are accumulated in p-type body
Data Source
AI summary
There is provided a semiconductor device including a capacitorless RAM. The semiconductor device includes a field effect transistor (FET) having a floating body structure. FET includes a channel body region arranged in a first region comprising a first semiconductor (e.g., p-SiGe) having a given band gap and a second region comprising a second semiconductor (e.g., n-Si) having a larger band gap than the first semiconductor.