Strained Channel Transistor via Deep Carbon Implantation
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Solution Overview
Problem
Existing methods for enhancing charge carrier mobility in transistors, such as strained silicon/germanium layers and stressed dielectric materials, face challenges like complex process techniques, reduced efficiency due to stress transfer mechanisms, and limitations in device geometry, particularly during aggressive device scaling.
Innovation Solution
The introduction of a silicon/carbon mixture or alloy as a strain-inducing region, formed through ion implantation and annealing, creates compressive or tensile strain in the channel region of transistors, enhancing performance without the complexity of selective epitaxial growth or sophisticated patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained silicon/germanium layers are used to enhance charge carrier mobility, then charge carrier mobility is improved, but process complexity increases due to selective epitaxial growth requirements
Solution Approach 1:
The patent changes the material composition parameter by introducing carbon into the silicon lattice to form silicon-carbon alloy regions. This parameter change induces strain in the channel region, enhancing charge carrier mobility without requiring complex selective epitaxial growth processes. The carbon concentration is controlled to achieve desired strain levels while maintaining compatibility with standard CMOS fabrication.
Solution Approach 2:
The patent extracts the strain-inducing function from complex multi-layer strained silicon/germanium structures and implements it through a simpler silicon-carbon alloy region. By taking out the germanium component and replacing it with carbon, the process complexity is reduced while maintaining the strain effect needed for improved charge carrier mobility.
2Reliability
If stressed dielectric materials are positioned close to transistor structures to create strain, then strain is induced in the channel region, but stress transfer efficiency is reduced due to intervening structures
Solution Approach 1:
The patent moves the strain-inducing mechanism from a lateral position (stressed dielectric materials positioned above or beside the channel) to a vertical position (silicon-carbon alloy region formed directly below the channel region). This dimensional change eliminates stress transfer losses through intervening structures like spacers and gate electrodes, as the strain is induced directly at the channel interface.
Solution Approach 2:
The silicon-carbon alloy region acts as an intermediary that directly couples the strain effect to the channel region. Instead of relying on stressed dielectric materials that require stress transfer through multiple interfaces, the silicon-carbon alloy serves as a direct mediator, inducing strain in the silicon channel through lattice mismatch at the immediate interface.
3Speed
If transistor dimensions are continuously shrunk to increase operating speed, then operating speed is improved, but short channel effects increase reducing channel controllability
Solution Approach 1:
The patent applies local quality by creating a silicon-carbon alloy region with specific strain characteristics directly beneath the channel region, while leaving other parts of the transistor structure unchanged. This localized strain induction enhances charge carrier mobility in the channel without affecting the overall transistor dimensions, allowing continued scaling while maintaining channel controllability through improved conductivity.
4Reliability
If complex patterning and deposition techniques are used to form strain-inducing regions, then strain transfer efficiency is improved, but device geometry flexibility is reduced during aggressive scaling
Solution Approach 1:
The silicon-carbon alloy region serves multiple functions: it induces strain in the channel region, maintains compatibility with standard CMOS fabrication processes, and can be formed using existing ion implantation and annealing techniques. This multi-functionality allows the strain-inducing structure to adapt to various device geometries and scaling requirements without requiring specialized patterning or deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides efficient strain transfer directly adjacent to the channel region, improving transistor performance with reduced process complexity and flexibility in adjusting strain types, while maintaining PN junction characteristics.
Implementation Method 1
implanting a carbon species proximate to, and in one embodiment below, a channel region of a first transistor to form a first strain-inducing area
Implementation Method 2
performing an anneal process for re-crystallizing the first strain-inducing area to create a compressive strain in the channel region of the first transistor
Data Source
AI summary
By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements.