Carbon Nanotube Memory Devices for Multi-Bit Storage
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Solution Overview
Problem
Current semiconductor memory devices, particularly nonvolatile memory devices, face limitations in integration density and capacity due to their manufacturing processes, and are unable to form three-dimensional structures for multi-bit operations.
Innovation Solution
The use of carbon nanotubes as channels in memory devices, with specific configurations including stacked storage nodes and gate electrodes, allows for multi-bit operations by applying distinct voltages to control data writing, erasing, and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional doping-based channels are used in planar memory devices, then manufacturing processes are simple, but integration density and capacity are limited
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical structures by stacking multiple memory cells vertically. Multiple storage nodes and gate electrodes are arranged in stacked configurations, enabling multi-bit operations per vertical column and significantly increasing integration density without expanding the planar footprint.
Solution Approach 2:
The patent employs carbon nanotubes as channel materials instead of traditional silicon-based doped channels. Carbon nanotubes provide superior electrical properties and enable the formation of complex three-dimensional structures with multiple storage nodes and gate electrodes, achieving both high integration density and multi-bit operational capability.
2Adaptability or versatility
If planar structure memory devices are used, then device structure is simple, but multi-bit operations cannot be performed
Solution Approach 1:
The patent implements multi-bit operations by stacking multiple storage nodes and gate electrodes vertically. Each stack contains multiple memory cells that can be independently controlled through selective voltage application to different gate electrodes, enabling simultaneous multi-bit read/write operations in a single vertical column.
Solution Approach 2:
The memory device is segmented into multiple independently controllable memory cells within each vertical stack. Each memory cell can be addressed individually through selective voltage application to specific gate electrodes, enabling parallel multi-bit operations by dividing the storage function across multiple segmented cells.
3Quantity of substance
If traditional nonvolatile memory structures are used, then manufacturing is established, but capacity is limited due to process limits
Solution Approach 1:
The patent achieves increased storage capacity by utilizing the vertical dimension through stacked memory cell structures. Multiple storage nodes are arranged vertically rather than laterally, allowing significantly more storage elements to be packed into the same planar area, thereby increasing overall capacity without being constrained by traditional lateral scaling limits.
Data Source
AI summary
A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.