Nanoinformatics TRIZ Cases

Mirror finishing the lateral end wall of a low-expansion glass substrate prevents glass fragment generation and reduces foreign particles in EUV lithography.

A multi-layer oxynitride charge storing layer uses distinct stoichiometries to trap and hold electrical charges in semiconductor memory devices.

A transistor with a graphene base layer reduces transit time and overcomes high base resistance limits.

Capillary filling of a reversed template prevents underlying layer damage during sparse pattern formation.

A material stack with alternating silicon etch stop and germanium template layers forms suspended nanowires over a notched substrate.

Constricted write wires apply spin-polarized current to move domain walls, resolving fabrication complexity while enabling high-density data access.

Segmenting the gate structure decouples shadowed material removal from line definition, resolving isotropic etching precision issues.

A spin control electronic device uses a triangular low-dimensional nanostructure to inject spin-polarized electrons into the transfer channel.

An auxiliary magnetic layer with a smaller aspect ratio reduces the switching field and minimizes variations in miniaturized memory cells.

Double complex salt oligomers absorb light across visible to near-infrared ranges through high molar extinction coefficients.

An inert atmosphere eliminates ambient air trapped in photoresist during substrate embossing, preventing gas inclusion defects.

Stacked organic photodetector subcells span ultraviolet to near-infrared wavelengths through segmented donor-acceptor heterojunctions.

A resin mold with a fluorine concentration gradient resolves the trade-off between substrate adhesion and release durability in nanoimprint lithography.

Metal-doped zinc oxide electron transport layer improves conversion efficiency while preventing cathode peeling in organic photoelectric devices.

A dual photolithography and etch sequence defines hard mask mandrels and spacers to establish independent critical dimensions for spin-transfer torque MRAM elements.

Segmenting the servo region into patterned areas with opposite magnetization directions stabilizes servo signals and improves reading accuracy.

Graphene channels and carbon nanotube gates eliminate metal pollution while maintaining electrical reliability.

A multi-layered bipolar field-effect transistor uses a titanium suboxide separating layer to isolate electron and hole transport channels.

Hydrogen flow scatters high-energy ions to protect the mirror coating, extending lifetime beyond one year of manufacturing operation.

Bis-(8-quinolinolato-N,O)platinum (II) complexes form crystalline thin films to absorb light and transport charges in organic photovoltaic devices.

A stress adjustment layer induces compressive strain in a semiconductor device channel through elastic relaxation.

Suspended nanowire gate-all-around FETs form on bulk substrates via sacrificial spacer oxidation, eliminating expensive SOI costs.

An NEM relay pass-gate eliminates off-currents and reduces variability, enabling sub-1V operation and smaller capacitors.

Nanocrystalline organic active layers form high conductivity networks, reducing series resistance in disordered structures to boost power conversion efficiency.

Stacked SiGe channels in GAA FETs improve read speeds while reducing leakage currents.

Isotropic etching removes resist sidewall material to prevent physical damage and process defects in high-resolution lift-off patterning.

A photovoltaic device uses a semiconducting bilayer of complementary metallophthalocyanine polymorphs to broaden light absorption.

Sacrificial spacers define sub-lithographic gaps between semiconductor structures, resolving lithography precision limits.

A process model fits uncalibrated mask error terms using measured critical dimensions and aerial image sensitivity coefficients.

Dipole areal densities in gate insulators differentiate lower transistor thresholds, avoiding complex patterning and high-temperature annealing damage.

Varying drain-source bias voltages across quantum dot-graphene field effect transistors creates unique scrambled signals to prevent unauthorized access.

Exposed silicon (111) planes enable label-free detection of specific reagents by measuring electrical conductivity changes.

A quantum dot channel field-effect transistor uses a superlattice structure to enable multi-bit logic operations.

Segmenting the storage medium into multiple movers allows probes to access smaller data zones simultaneously, reducing seek times and boosting random IOPS.

A method co-integrates junction field effect transistors with vertical field effect transistors on a single substrate using shared gate regions and simultaneous fin formation.

Stacked storage nodes on a carbon nanotube channel resolve integration density limits by enabling multi-bit operations within a compact vertical footprint.

A resin coating unit deposits material across multiple shot areas to enable continuous pattern transfer operations.

Oxide channel areas insulate nanowire segments to form 2-5 nm quantum dots, resolving manufacturing precision limits in gate-all-around transistors.

A dual-core quantum rod separates emission cores to enable independent electric field control of optical properties.

Suction-based mechanics replace mechanical pressure to prevent substrate deformation while radiation detection tracks material flow completion.

Self-limited etch stops enable uniform spacer formation, resolving insufficient lateral etching budgets that degrade gate control.

A curable composition layer with controlled particle concentration and surface tension spreads rapidly across a substrate.

Removing first isolation layers creates gaps for complete sacrificial layer extraction, expanding channel region area and increasing operating currents.

Epitaxial growth creates a halo region physically separated from the gate dielectric, eliminating residual implantation atoms that compromise reliability.

Self-assembled organic linkers position metal ions for uniform nanoparticle growth, enabling room temperature operation without complex lithography equipment.

Directional etch forms shoulder regions in memory holes to reduce misalignment errors and improve manufacturing yield.

Selective polymer vaporization reduces imprint structure dimensions without expensive molds, avoiding etching defects and improving throughput.

Merging photoelectric conversion and filtering via organic electrode layers increases light sensitivity while reducing false-color artifacts in imaging devices.

Unclamp substrates between patterning steps to relieve accumulated strain and prevent pattern misalignment.