Co-integrating JFETs into Vertical FETs
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in integrating junction field effect transistors (JFETs) into vertical field effect transistor (VFET) device architecture, particularly in reducing lateral dimensions and optimizing source-to-channel link-up, while maintaining high performance and density.
Innovation Solution
A method and structure for co-integrating JFETs into VFETs on the same substrate, where the processes for forming fins and channel regions occur simultaneously, allowing shared gate regions and optimized contact structures to enhance performance and density, with the JFET channel region thickness being greater than the VFET fins, enabling both low-voltage and high-voltage transistor devices on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate fabrication processes are used for JFET and VFET, then each device can be optimized independently, but manufacturing complexity and process time increase
Solution Approach 1:
The patent combines the fabrication processes for JFET and VFET into a single integrated process flow. The method forms both device types simultaneously on the same substrate using shared process steps including fin formation, channel region creation, spacer deposition, and gate formation, thereby reducing manufacturing complexity while maintaining device performance optimization
Solution Approach 2:
The fabrication process is designed to be universal, accommodating both JFET and VFET device architectures through the same sequence of manufacturing steps. The process can selectively form different device types in different regions of the substrate while using identical process equipment and methodologies
2Reliability
If JFET channel region thickness is increased for high-voltage applications, then voltage handling capability improves, but lateral dimensions and device footprint increase
Solution Approach 1:
The patent transitions from planar JFET structures to vertical JFET architectures where the channel extends vertically through fins rather than laterally. This dimensional change allows the channel region to achieve sufficient thickness for high-voltage operation while maintaining a compact lateral footprint, as the current flow path is redirected to the vertical dimension
Solution Approach 2:
The patent employs composite material structures including silicon fins with controlled doping profiles and integrated spacer regions that provide both mechanical support and electrical isolation. The combination of differently doped regions and material layers enables high-voltage capability without proportionally increasing device area
3Speed
If VFET narrow channel length is used for rapid switching, then switching speed improves, but current-carrying capacity decreases
Solution Approach 1:
The patent utilizes vertical channel structures where the channel length is defined in the vertical dimension rather than laterally. This allows narrow effective channel lengths for rapid switching while maintaining adequate cross-sectional area through fin width and multi-fin configurations to sustain high current-carrying capacity
Solution Approach 2:
The patent employs multiple parallel fins to segment the current path, allowing each fin to have a narrow channel length for fast switching while the aggregate of multiple fins provides sufficient total current-carrying capacity. The segmented structure distributes current across multiple channels
Data Source
AI summary
Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.