Stress Induction in 3D Device Channel via Elastic Relaxation
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Solution Overview
Problem
Current methods face challenges in inducing compressive stress in semiconductor devices, which is crucial for enhanced performance, especially for p-type field effect transistors, as traditional external stressors and relaxed SiGe buffers are inadequate.
Innovation Solution
A stress adjustment layer with a different crystal lattice parameter is formed on a substrate, and etched to release stress, inducing compressive strain in the device channel layer, which can include materials like Si3P4 or SiC to achieve the necessary compressive stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If traditional external stressors or relaxed SiGe buffers are used to induce stress in the channel, then tensile stress can be achieved, but compressive stress cannot be effectively induced
Solution Approach 1:
Instead of directly applying compressive stress to the channel, the patent uses a stress adjustment layer with tensile stress that, when relaxed, indirectly induces compressive stress in the channel. This inversion approach allows compressive stress induction without requiring direct compressive stressors.
Solution Approach 2:
The stress adjustment layer acts as an intermediary between the substrate and the channel. It has a different crystal lattice parameter than the substrate, creating as-deposited tensile stress that transfers to the channel upon relaxation, enabling compressive stress in the channel without direct contact with compressive stressors.
2Stress or pressure
If SiGe layers are used above critical thickness to induce stress, then stress can be achieved, but device defects increase
Solution Approach 1:
The patent changes the material parameter (crystal lattice parameter) of the stress adjustment layer to create as-deposited tensile stress. By selecting materials with appropriate lattice mismatch, stress is induced without requiring thick layers that would cause defects. The stress adjustment layer can be thinner and more reliable while achieving the same stress effect.
3Stress or pressure
If high thermal budget processes are applied to SiGe layers, then stress can be induced, but layer defects increase
Solution Approach 1:
The stress adjustment layer is designed to have as-deposited tensile stress built-in during deposition, eliminating the need for subsequent high thermal budget processes to induce stress. This preliminary action preserves layer integrity and reduces defects while achieving the desired channel stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively induces compressive stress in semiconductor devices, improving the performance of p-type field effect transistors by altering the lattice constant and providing a viable alternative to traditional stressors.
Implementation Method 1
Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer
Implementation Method 2
The device channel layer includes a compressive stress induced by stress relaxation of the stress adjustment layer
Implementation Method 3
the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate
Data Source
AI summary
A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source/drain regions are formed adjacent to the device channel layer.