Gate-All-Around MOSFET Fabrication via Sacrificial Layer Removal
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Solution Overview
Problem
The electrical performance of existing Gate-All-Around (GAA) structure MOSFETs needs improvement due to limitations in increasing operating currents, primarily because the channel region volume is restricted, leading to inefficiencies in channel coverage and leakage currents.
Innovation Solution
A fabrication method involving the formation of fin structures with sacrificial layers and isolation layers, where a first isolation layer is removed to create gaps between second isolation layers and adjacent fins, allowing complete removal of sacrificial layers and enabling a gate structure to surround channel layers from four sides, thereby increasing the channel region area and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a conventional FinFET structure is used, then the manufacturing process is simpler, but the channel region volume is small and operating currents are limited
Solution Approach 1:
The patent transitions from planar 2D gate coverage to 3D gate-all-around structure, where the gate electrode wraps around the channel region in multiple dimensions. This is achieved by forming sacrificial layers at specific positions that guide the deposition of gate dielectric and gate electrode materials, enabling the gate to surround the channel from top, bottom, and sidewalls, thereby maximizing channel region volume utilization.
Solution Approach 2:
The gate structure is segmented into multiple components: gate dielectric layer, gate electrode layer, and metal interconnect layers, each formed through separate deposition and patterning steps. The sacrificial layers are also segmented and positioned at specific locations to enable selective removal and formation of the all-around gate structure, allowing complex 3D geometry to be built through sequential simpler steps.
2Manufacturing precision
If the gate structure is formed to surround channel layers completely, then the channel coverage is improved, but the sacrificial layers may not be completely removed leading to defects
Solution Approach 1:
The patent introduces a first isolation layer as an intermediary between the sacrificial layers and the gate structure formation process. This isolation layer is formed at specific positions, removed selectively to create gaps, and then used as a reference for forming the gate structure. The intermediary layer enables complete removal of sacrificial layers by providing a pathway and preventing damage to surrounding structures during the removal process.
Solution Approach 2:
The first isolation layer is formed preliminarily before gate structure formation, with specific patterns designed to facilitate subsequent sacrificial layer removal. The isolation layer is removed in advance to create gaps that enable access to and complete removal of sacrificial layers, preventing any residual material from compromising the gate structure alignment and reliability.
3Measurement precision
If photomask etching is used to form gate openings, then the pattern precision is improved, but the process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and removes the first isolation layer selectively from the structure, creating gaps without requiring photomask etching of the gate opening pattern itself. This extraction approach simplifies the fabrication process by eliminating complex photolithography steps while maintaining precise gate opening patterns through the self-aligned nature of the isolation layer removal and subsequent gate material deposition.
Data Source
AI summary
A fabrication method of a semiconductor structure is provided. The method includes: providing a substrate; forming fin structures on the substrate along a first direction with isolation grooves between adjacent fin structures, where each fin structure includes sacrificial layers stacked along a normal direction of the substrate and a channel layer between every two adjacent sacrificial layers; forming a first isolation layer in each isolation groove; forming a second isolation layer at a surface of each first isolation layer to fill up a corresponding isolation groove; forming a dummy gate structure; removing first isolation layers; removing the dummy gate structure to form a gate opening at ends of the sacrificial layers along a second direction perpendicular to the first direction; removing the sacrificial layers to form gate grooves between adjacent channel layers; and forming a gate structure in the gate opening and the gate grooves surrounding the channel layers.