Gate-All-Around Nanowire FETs on Bulk Substrates
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Solution Overview
Problem
The high cost of semiconductor-on-insulator (SOI) substrates limits the widespread adoption of gate-all around semiconductor nanowire field effect transistors, prompting the need for a cost-effective alternative using bulk semiconductor substrates.
Innovation Solution
A method is developed to form gate-all around semiconductor nanowire field effect transistors on bulk semiconductor substrates by creating semiconductor nanowires with end segments attached to pad regions, using a sacrificial spacer, oxidation process, and hydrogen anneal to form suspended nanowires with a gate surrounding the central portion, and source and drain regions on opposite sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI substrates are used to form gate-all around semiconductor nanowire FETs, then device performance and non-planar structure are achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent extracts the semiconductor nanowire from the SOI substrate structure, forming suspended nanowires on bulk substrates. The nanowires are released from the substrate using sacrificial layer removal, creating the gate-all-around structure without requiring expensive SOI substrates. This maintains device performance while reducing manufacturing cost.
Solution Approach 2:
The patent uses sacrificial layers (such as silicon dioxide or silicon nitride) that are temporarily introduced during fabrication and then completely removed. These disposable sacrificial structures enable the formation of suspended nanowires on cost-effective bulk substrates, replacing the need for expensive SOI substrates while maintaining the required device performance.
2Ease of manufacture
If bulk semiconductor substrates are used instead of SOI substrates, then manufacturing cost decreases, but forming suspended nanowires with proper gate-all-around structure becomes more difficult
Solution Approach 1:
The patent incorporates the sacrificial layer formation and nanowire definition steps early in the fabrication process, before the complex gate-all-around structure formation. The sacrificial layers are strategically placed and patterned in advance, enabling subsequent straightforward nanowire release and gate formation. This preliminary structuring simplifies the overall process despite using bulk substrates.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that mediate between the bulk substrate and the final suspended nanowire configuration. These intermediary sacrificial structures enable the transformation from planar bulk substrate to three-dimensional suspended nanowire geometry, facilitating the gate-all-around formation without requiring complex direct processing of bulk substrates.
3Manufacturing precision
If nanowires are suspended above the substrate, then gate-all-around control is achieved, but additional process steps and structural complexity are introduced
Solution Approach 1:
The patent segments the nanowire structure from the substrate by removing the sacrificial layer beneath the nanowire. This segmentation creates the suspended configuration that enables complete gate surround, providing superior electrostatic control. The nanowire is divided into suspended sections and anchored sections, allowing precise gate control while managing structural complexity through systematic segmentation.
Solution Approach 2:
The patent transitions the nanowire from a planar configuration on the substrate to a three-dimensional suspended structure. This dimensional change allows the gate to surround the nanowire completely in all directions, achieving gate-all-around control. The vertical suspension provides the additional spatial dimension needed for complete gate enclosure, enhancing control precision despite increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a cost-effective means to produce gate-all around semiconductor nanowire FETs without the need for SOI substrates, enabling efficient fabrication of non-planar semiconductor devices while maintaining device performance.
Implementation Method 1
An oxidation process is then performed which converts a recessed surface of the bulk semiconductor substrate into a horizontal semiconductor oxide portion, while converting the vertical semiconductor pillar portion into a vertical semiconductor oxide pillar portion
Implementation Method 2
Next, a hydrogen anneal is performed on the at least one suspended semiconductor nanowire
Data Source
AI summary
Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.